Synthesis of real-time recursive DSP algorithms using multiple chips

In this paper, the problem of synthesizing real-time recursive DSP algorithms with fixed interprocessor communication delay is addressed. The effects of the communication delay to the initiation interval and number of chips are studied. We differentiate our problem from previous work in two parts. First, the DSP algorithms we consider are recurrence. Second, communication delay is considered. By modifying previously proposed scheduling and allocation algorithm, we are able to derive an implementation if it exists under the given real-time and area constraints. Some experiments have been made and results are very promising.