Macromodeling C- and RC-loaded CMOS inverters for timing analysis

Abstract

Timing macromodels for a CMOS inverter loaded by a capacitor or by a series-resistor shunt-capacitor circuit are derived and verified. The macromodel for the capacitive load case is a simple analytical function of a single variable which combines input wave shape, capacitive load, and transistor drive. The model for the RC case is a combination of lookup table and analytical function yielding excellent accuracy to within 5% of detailed circuit simulation.