2007 IEEE Asian Solid-State Circuits Conference最新文献_第6页

Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect 设计90nm 4 cpu 4320MIPS SoC，具有单独管理频率和2.4GB/s多主片上互连

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425785

O. Nishii, I. Nonomura, Y. Yoshida, K. Hayase, S. Shibahara, Y. Tsujimoto, M. Takada, T. Hattori

{"title":"Design of a 90nm 4-CPU 4320MIPS SoC with individually managed frequency and 2.4GB/s multi-master on-chip interconnect","authors":"O. Nishii, I. Nonomura, Y. Yoshida, K. Hayase, S. Shibahara, Y. Tsujimoto, M. Takada, T. Hattori","doi":"10.1109/ASSCC.2007.4425785","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425785","url":null,"abstract":"We have developed a 97.6 mm2 SoC that includes four SuperHtrade architecture CPUs and a DDR-2 controller with 90-nm CMOS for high-performance embedded applications. These four 600 MHz CPUs are identical and each has a floating point unit, 32/32 KB cache memory, and 152 KB local memory. CPUs totally achieve performance of 4320MIPS. Main on-chip 300 MHz 64-bit bus manages processors access and another dedicated connection holds cache coherency operation. Considering varying processing load, this chip targets both low power consumption (proportional to processing load), and constant on-chip bandwidth. Each processor can be operated different frequencies while keeping on-chip bus frequency constant. With utilizing this individual core clock distribution scheme, the following designs have been developed: (i) frequency transition control that permits on-chip bus access of other bus master, (11) light-sleep mode that maintains cache coherency control, (iii) cache snoop control logic that holds cache coherency between multiple frequency processors. The main on-chip interconnect (bus) connects four-processor and other on-chip IPs. The numbers of access master and access slave increase due to processor number. Standard-Vth (against high-Vth) cell usage and layout control achieved 300-MHz multi-master operation.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126207693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

An all-digital reused-SAR delay-locked loop with adjustable duty cycle 具有可调占空比的全数字复用sar延时锁环

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425693

Wei-Ming Lin, Shen-Iuan Liu

引用次数: 3

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement 一种硬件效率为0.13μm的基于概率的容噪电路设计与实现，抗噪能力提高24.5dB

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425694

I-Chyn Wey, You-Gang Chen, Changhong Yu, Jie Chen, A. Wu

引用次数: 10

1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices 1.8mW，混合流水线H.264/AVC解码器，用于移动设备

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425763

Sangkwon Na, Woong Hwangbo, Jaemoon Kim, Seunghan Lee, C. Kyung

引用次数: 11

A uniform bandwidth PLL using a continuously tunable single-input dual-path LC VCO for 5Gb/s PCI express Gen2 application 采用连续可调单输入双路LC压控振荡器的均匀带宽锁相环，适用于5Gb/s PCI express Gen2应用

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425732

W. Rhee, H. Ainspan, D. Friedman, T. Rasmus, S. Garvin, C. Cranford

引用次数: 17

UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC UltraSPARC T2:一款高性能、高能效的SPARC SOC

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425786

Manish Shah, Jama Barreh, J. Brooks, R. Golla, G. Grohoski, N. Gura, Ricky C. Hetherington, Paul J. Jordan, Mark Luttrell, Christopher H. Olson, Bikram Saha, Denis Sheahan, Lawrence Spracklen, Aaron Wynn

{"title":"UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC","authors":"Manish Shah, Jama Barreh, J. Brooks, R. Golla, G. Grohoski, N. Gura, Ricky C. Hetherington, Paul J. Jordan, Mark Luttrell, Christopher H. Olson, Bikram Saha, Denis Sheahan, Lawrence Spracklen, Aaron Wynn","doi":"10.1109/ASSCC.2007.4425786","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425786","url":null,"abstract":"UltraSPARC T2 is Sun Microsystems' second generation multi-core, multi-threaded SPARC System-on-a-chip. It delivers twice the throughput performance of the first generation UltraSPARC T1 processor in essentially the same power envelope. UltraSPARC T2 supports concurrent execution of 64 threads by utilizing eight SPARC cores, each with eight hardware threads. The cores communicate via a high bandwidth crossbar and share a 4 MB, eight bank, L2 cache. Each SPARC core includes two integer execution units and a dedicated floating point and graphics unit, which delivers a peak floating point throughput of 11.2 GFLOPS/sec at 1.4 GHz. Each core also has a cryptographic unit. For I/O, UltraSPARC T2 has an integrated x8 PCI-Express channel and two 10 G Ethernet ports with XAUI interfaces. Memory is accessed via four on-chip controllers each controlling 2 FBDIMM channels for a peak memory bandwidth in excess of 60 GB/sec. UltraSPARC T2 is fabricated in an 11 metal, 1.1 V, triple-Vt CMOS process. The chip has ~500 M transistors on a 342 mm2 die with a power consumption of 84 W at 1.4 GHz. The high level of system integration along with high throughput, floating point, and cryptographic performance makes UltraSPARC T2 an ideal choice for a range of applications including webservers, database and applications servers, high performance computing, secure networking, campus backbones, and file servers.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127868365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 117

A multi matrix-processor core architecture for real-time image processing SoC 用于实时图像处理SoC的多矩阵处理器核心架构

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425760

K. Mizumoto, T. Tanizaki, S. Kobayashi, M. Nakajima, T. Gyohten, H. Yamasaki, H. Noda, M. Higashida, Y. Okuno, K. Arimoto

引用次数: 5

A PCI-express Gen2 transceiver with adaptive 2-Tap DFE for up to 12-meter external cabling PCI-express Gen2收发器，具有自适应2-Tap DFE，可用于长达12米的外部电缆

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425788

T. Yeh, Wei-Yu Wang, Wen-Liang Wang, Yu-Hong Lin, Ying-Lien Cheng, Tsung-Hsin Chou, Jyhfong Lin

引用次数: 2

Where is Korea’s fabless semiconductor industry headed? 韩国无晶圆厂半导体产业将走向何方?

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425783

J. Hwang

引用次数: 1

A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-µm CMOS 一个480-MHz至1 ghz的亚皮秒时钟发生器，在0.13µm CMOS中具有快速准确的自动频率校准

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425733

Joonhee Lee, Kyunglok Kim, Junghyup Lee, Taekwang Jang, Seonghwan Cho

引用次数: 27