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An optimal design of high performance interface circuit with acoustic transducer model 基于声换能器模型的高性能接口电路优化设计
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425685
Yu-Chun Hsu, Jen-Yi Chen, T. Mukherjee, G. Fedder
{"title":"An optimal design of high performance interface circuit with acoustic transducer model","authors":"Yu-Chun Hsu, Jen-Yi Chen, T. Mukherjee, G. Fedder","doi":"10.1109/ASSCC.2007.4425685","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425685","url":null,"abstract":"Reducing interface circuit power consumption without compromising low noise performance is an increasing challenge for portable sensor applications. Thus paper reports a high power efficiency and high SNR capacitive MEMS microphone interface circuit using a negative feedback amplifier. The transistors in the interface circuit are biased in the deep subthreshold region, for a 45% better figure of merit (FoM) that considers both noise and power. The MEMS microphone mechanical behavior is modeled using an analog hardware description language to enable co-simulation of the microphone together with the circuit. This co-simulation platform enables optimization of the MEMS microphone simultaneously with the interface circuit.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129693800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Backgate bias accelerator for 10ns-order sleep-to-active modes transition time 用于10ns阶睡眠到活动模式转换时间的后门偏置加速器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425689
D. Levacq, M. Takamiya, T. Sakurai
{"title":"Backgate bias accelerator for 10ns-order sleep-to-active modes transition time","authors":"D. Levacq, M. Takamiya, T. Sakurai","doi":"10.1109/ASSCC.2007.4425689","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425689","url":null,"abstract":"Backgate biasing is a promising technique for high-speed systems. Leakage can be reduced during standby periods by reverse bias while adequate bias in active mode can balance process and temperature variations. This technique introduces no delay penalty in active mode but slow wake up time results in system performance degradation. In this paper, a backgate bias accelerator achieving 24 ns/V sleep-to-active mode transition rate is demonstrated in a 90 nm CMOS technology. The circuit performs auto-calibration of the transition time as a function of the sleep and active mode backgate bias voltages. Those can therefore be tuned on-chip according to process variations and/or operating conditions. The accelerator occupies less than 2.5% of the total chip area, consumes 600 muW during the transitions and doesn't add any bias current during active and sleep modes.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A GHz-digital clock jitters in time and frequency ghz数字时钟在时间和频率上抖动
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425695
D.D. Kim, Jonghae Kim, Choongyeun Cho, D. Lim
{"title":"A GHz-digital clock jitters in time and frequency","authors":"D.D. Kim, Jonghae Kim, Choongyeun Cho, D. Lim","doi":"10.1109/ASSCC.2007.4425695","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425695","url":null,"abstract":"The GHz-digital clock jitter measurement capabilities in time and frequency domains are explored. A 101-stage inverter-based ring oscillator implemented in 65 nm SOI is used as a clock source. Both domains produce clock period jitters reliably. Cycle-to-cycle jitters are obtained in time, and confirmed In frequency domain. Time interval error jitters are calculated from phase noise, and time-domain results are matched with frequency-dependent jitters. The convergence and limitations of time and frequency-domain jitter measurements are presented.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134074343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 2.5Gb/s ESD-protected dual-channel optical transceiver array 2.5Gb/s防静电双通道光收发器阵列
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425754
Jung-Won Han, Boo-Young Choi, Kang-Yeob Park, W. Oh, Sung Min Park
{"title":"A 2.5Gb/s ESD-protected dual-channel optical transceiver array","authors":"Jung-Won Han, Boo-Young Choi, Kang-Yeob Park, W. Oh, Sung Min Park","doi":"10.1109/ASSCC.2007.4425754","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425754","url":null,"abstract":"This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18 mum CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5 Gb/s, equipped with the APC (5-15 mA) and AMC (4-20 mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87 dBOmega transimpedance gain, 1.4 GHz bandwidth for 2 pF input parasitic capacitance, -18 dBm sensitivity for 10-12 BER, and less than -20 dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500 mW.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134267525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution 频率分辨率为5kHz的3.3 GHz lc型数字控制振荡器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425722
J. Zhuang, Q. Du, Tad Kwasniewski
{"title":"A 3.3 GHz LC-based digitally controlled oscillator with 5kHz frequency resolution","authors":"J. Zhuang, Q. Du, Tad Kwasniewski","doi":"10.1109/ASSCC.2007.4425722","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425722","url":null,"abstract":"This paper reports a LC-based digitally controlled oscillator (DCO) with an enhanced frequency resolution and an extended linear frequency tuning range. It has a center frequency of 3.3 GHz. and a frequency tuning range of 600 MHz covered by 64 different frequency bands. Each frequency band has 2048 linear tuning levels with a frequency step of 5 kHz. This DCO was implemented in 90 nm CMOS and the measured frequency tuning characteristics arc provided in this paper. The DCO exhibits a phase noise of -11 NdBc/Hz. at 1 MHz frequency offset. The DCO core consumes 2 mA current from 1.2 V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134310928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
A 9 GHz dual-mode digitally controlled oscillator for GSM/UMTS transceivers in 65 nm CMOS 一种用于65纳米CMOS GSM/UMTS收发器的9 GHz双模数字控制振荡器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425723
Y. Chen, V. Neubauer, Y. Liu, U. Vollerbruch, C. Wicpalek, T. Mayer, B. Neurauter, L. Maurert, Z. Boos
{"title":"A 9 GHz dual-mode digitally controlled oscillator for GSM/UMTS transceivers in 65 nm CMOS","authors":"Y. Chen, V. Neubauer, Y. Liu, U. Vollerbruch, C. Wicpalek, T. Mayer, B. Neurauter, L. Maurert, Z. Boos","doi":"10.1109/ASSCC.2007.4425723","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425723","url":null,"abstract":"A 9 GHz fully digitally controlled oscillator implemented in 65 nm CMOS technology is presented. This is the first DCO implemented at 9 GHz which covers all transmitter (TX) and receiver (RX) bands of GSM/EDGE and UMTS except Band VII. It covers a coarse tuning range from 6.35 GHz to 9.15 GHz which is realized by binary weighted switchable capacitors. The phase noise performance meets the specifications of GSM/EDGE and UMTS with a low current consumption.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133494496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing 采用电容和运放共享的1.8V 36mw 11位80MS/s流水线ADC
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425775
N. Sasidhar, Youn-Jae Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, U. Moon
{"title":"A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing","authors":"N. Sasidhar, Youn-Jae Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. Hanumolu, U. Moon","doi":"10.1109/ASSCC.2007.4425775","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425775","url":null,"abstract":"A new capacitor and opamp sharing technique that enables a very efficient low power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back in the absence of sample and hold is also presented. Fabricated in a 0.18-mum CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which analog portion consumes 24 mW.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129350395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 470-μw multi-modulus injection-locked frequency divider with division ratio of 2, 3, 4, 5 and 6 in 0.13-μm CMOS 基于0.13 μm CMOS的470 μw多模注入锁定分频器，分频比分别为2、3、4、5和6
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425698
Joonhee Lee, Seonghwan Cho
{"title":"A 470-μw multi-modulus injection-locked frequency divider with division ratio of 2, 3, 4, 5 and 6 in 0.13-μm CMOS","authors":"Joonhee Lee, Seonghwan Cho","doi":"10.1109/ASSCC.2007.4425698","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425698","url":null,"abstract":"This paper presents a multi-modulus injection-locked frequency divider (ILFD) based on a ring oscillator using inverter chains for a small area and low power consumption. In the proposed ILFD, division ratio of 2, 3, 4, 5 and 6 can be performed by selecting a specific loop which consists of a transmission gate and several delay cells. A prototype chip implemented in 0.13 mum CMOS process operates at 5 GHz while consuming 470 muW from 1.2 V supply, where 350 muW is dissipated in me core of the ILFD. The proposed ILFD is the first reported multi-modulus ILFD with a digitally controlled division ratio and the size of the ILFD is 44 times 33 mum2. This number is one of the smallest area that have been reported for a ILFD.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122082928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme 一种基于1ghz ota的低通滤波器，具有高速自动调谐方案
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425717
Tien-Yu Lo, C. Hung
{"title":"A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme","authors":"Tien-Yu Lo, C. Hung","doi":"10.1109/ASSCC.2007.4425717","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425717","url":null,"abstract":"A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126037555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 2.5-3.2GHz CMOS differentially-controlled continuously-tuned varactor-less LC-VCO 一种2.5-3.2GHz CMOS差分控制连续调谐无变元LC-VCO
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425744
Deyi Pi, Byung-Kwan Chun, P. Heydari
{"title":"A 2.5-3.2GHz CMOS differentially-controlled continuously-tuned varactor-less LC-VCO","authors":"Deyi Pi, Byung-Kwan Chun, P. Heydari","doi":"10.1109/ASSCC.2007.4425744","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425744","url":null,"abstract":"The design and implementation of a 2.5-3.2 GHz LC-VCO incorporating a varactor-less tuning technique is presented. The VCO's oscillation frequency is tuned differentially by varying the effective inductance of the oscillators. Fabricated in a 0.18 mum CMOS process, the prototype VCO achieves 24% continuous tuning range without varactors. The circuit draws 7-15 mA current from a 1.8 V power supply. The measured phase noise is varying between -102 dBc/Hz and -111 dBc/Hz at 1 MHz offset across the tuning range.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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