{"title":"一种基于1ghz ota的低通滤波器,具有高速自动调谐方案","authors":"Tien-Yu Lo, C. Hung","doi":"10.1109/ASSCC.2007.4425717","DOIUrl":null,"url":null,"abstract":"A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"23","resultStr":"{\"title\":\"A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme\",\"authors\":\"Tien-Yu Lo, C. Hung\",\"doi\":\"10.1109/ASSCC.2007.4425717\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"23\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425717\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425717","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme
A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.