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Bi-directional AC coupled interface with adaptive spread spectrum clock generator 双向交流耦合接口与自适应扩频时钟发生器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425734
Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa
{"title":"Bi-directional AC coupled interface with adaptive spread spectrum clock generator","authors":"Y. Komatsu, T. Ebuchi, Takashi Hirata, T. Yoshikawa","doi":"10.1109/ASSCC.2007.4425734","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425734","url":null,"abstract":"We propose a method of reducing a quantization noise and a spectrum peak utilizing an adaptive spread spectrum clocking PLL (SSC-PLL) circuit for bi-directional and AC coupled interface. To realize a high speed, wide range, bi-directional and long cable transceiver, we designed a test chip that contained an Equalizer, CDR, and differential transceiver for long cable, and also an SSC-PLL for reducing spectrum peak with jitter optimization by adaptive bandwidth setting. Utilize this interface, it can be realized up to 810 Mbps and 20-m bi-directional transceiver system with high ESD protection, and spectrum peak reduction about -23 dB effectively with an optimum bandwidth.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS 基于0.18 μm CMOS的0.05 mm2 110 μ w 10-b自校准逐次逼近ADC核心
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425771
Y. Kuramochi, A. Matsuzawa, M. Kawabata
{"title":"A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS","authors":"Y. Kuramochi, A. Matsuzawa, M. Kawabata","doi":"10.1109/ASSCC.2007.4425771","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425771","url":null,"abstract":"We present a 10-bit 1-MS/s successive approximation analog-to-digital converter core including a charge redistribution digital-to-analog converter and a comparator. A new linearity calibration technique enables use of a nearly minimum capacitor limited by kT/C noise. The ADC core without digital blocks has been fabricated in a 0.18-mum CMOS process and consumes 110muW at 1.8 V power supply. With the calibration it achieves 9.0-dB improvement of SNDR and 23.3dB improvement of SFDR. The measured SNDR and SFDR are 51.1 dB and 69.8 dB respectively.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128836621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector 采用基于窗口的鉴相器，具有4.6 ps RMS抖动的6.1 mw双环数字DLL
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425736
Paritosh Bhoraskar, Y. Chiu
{"title":"A 6.1-mW dual-loop digital DLL with 4.6-ps RMS jitter using window-based phase detector","authors":"Paritosh Bhoraskar, Y. Chiu","doi":"10.1109/ASSCC.2007.4425736","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425736","url":null,"abstract":"A 0.13-mum CMOS dual-loop digital DLL for multiphase clock generation and synchronization is presented. Ten clock phases are produced and locked to a first reference clock by the inner loop, while the outer loop further aligns all phases simultaneously to a second reference clock at a higher frequency. Unlike usual dual-loop DLLs, the proposed architecture has one loop completely enclosed inside the other, resulting in a second-order behavior. A window-based phase detection technique is exploited to minimize the circuit complexity and power with uncompromised jitter performance. The false-lock-free DLL operates over a wide frequency range of 0.2-1.2 GHz, measures a 4.6-ps rms jitter, and consumes 6.1 mW at 1.2 GHz.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115952187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 2.5V, 5mW UMTS and GSM dual mode decimation filter for sigma delta ADC 用于sigma delta ADC的2.5V, 5mW UMTS和GSM双模抽取滤波器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425683
Chi Zhang, E. Ofner
{"title":"A 2.5V, 5mW UMTS and GSM dual mode decimation filter for sigma delta ADC","authors":"Chi Zhang, E. Ofner","doi":"10.1109/ASSCC.2007.4425683","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425683","url":null,"abstract":"This paper describes a decimation processor for a dual-mode sigma-delta ADC for GSM and UMTS mobile standards. Partly contradictory requirements like high dynamic range and low bandwidth for GSM and vice versa for UMTS need decimation factors of M=144 (GSM) and M=8 (UMTS). A multi-rate filter architecture, which allows best hardware re-use for both mobile standards, is selected. Since the ADC is to be integrated into the power management component of the mobile terminal utilizing a 0.35 mum CMOS technology, special attention has been given to silicon area and power consumption of the component, while maintaining a standard design flow for the implementation. The processor covers 1.13 mm2 of silicon and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at Vdd=2.5 V.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114774318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 26.5–37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS 一个26.5-37.5 GHz分频器和一个73-GHz-BW CML缓冲器，0.13μm CMOS
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425752
Jeong-Kyoum Kim, Jaeha Kim, Sangyoon Lee, Suhwan Kim, D. Jeong
{"title":"A 26.5–37.5 GHz frequency divider and a 73-GHz-BW CML buffer in 0.13μm CMOS","authors":"Jeong-Kyoum Kim, Jaeha Kim, Sangyoon Lee, Suhwan Kim, D. Jeong","doi":"10.1109/ASSCC.2007.4425752","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425752","url":null,"abstract":"This paper presents a frequency divider with a wide operating frequency range and a high bandwidth CML buffer intended for an 80-Gb/s serial link system. The proposed divider uses a pulsed-latch architecture that replaces the slave latch in a flip-flop-based divider with a buffer. The CML buffer employs both shunt-and-double-series inductive peaking and active feedback. Implemented in a 0.13-mum CMOS process with fT of only 82 GHz, the divider operates over a wide range of 26.5-37.S GHz with an input sensitivity of 1 Vpp, diff and produces a nominal output swing of 1 Vpp, diff. The CML buffer achieves a -3 dB bandwidth of 73.5 GHz in simulation, which is high enough to buffer an 80-Gb/s NRZ data stream. The fabricated frequency divider and clock buffers dissipate 22.5 mW and 72 mW, respectively, from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128066472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors 用于便携式SoC处理器的低杂散14.4mW 1.8GHz CMOS fvc时钟发生器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425692
Gil-Su Kim, Chulwoo Kim, Soo-Won Kim
{"title":"A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors","authors":"Gil-Su Kim, Chulwoo Kim, Soo-Won Kim","doi":"10.1109/ASSCC.2007.4425692","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425692","url":null,"abstract":"A 60 MHz to 1.8 GHz frequency-to-voltage converter (FVC)-based clock generator is fabricated in a 0.18-mum CMOS process for portable SoC processors. The clock generator employs the FVC and a VCO to reduce power and jitter simultaneously, which achieves spurious tone of -54.1 dBc, rms jitter of 1.497 ps and peak-to-peak jitter of 14.4 mW at 1.8 V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127304894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique 一种基于平衡降噪技术的CMOS宽带低噪声放大器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425739
Youchun Liao, Zhangwen Tang, Hao Min
{"title":"A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique","authors":"Youchun Liao, Zhangwen Tang, Hao Min","doi":"10.1109/ASSCC.2007.4425739","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425739","url":null,"abstract":"A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124238619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
A 8-bit 500-KS/s low power SAR ADC for bio-medical applications 用于生物医学应用的8位500-KS/s低功耗SAR ADC
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425772
You-Kuang Chang, Chao-Shiun Wang, Chorng-Kuang Wang
{"title":"A 8-bit 500-KS/s low power SAR ADC for bio-medical applications","authors":"You-Kuang Chang, Chao-Shiun Wang, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2007.4425772","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425772","url":null,"abstract":"This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. An energy-saving switching sequence technique is proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 56% compared to a conventional switching method. The measured signal-to-noise-and-distortion ratios of the ADC is 46.92 dB at 500 KS/s sampling rate with an ultra-low power consumption of only 7.75-muW from a 1-V supply voltage. The ADC is fabricated in a 0.18-mum CMOS technology.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131538073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 169
Performance and power evaluation of SH-X3 multicore system SH-X3多核系统的性能与功耗评估
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425678
M. Takada, S. Shibahara, K. Hayase, T. Kamei, Y. Yoshida, K. Takada, N. Irie, O. Nishii, T. Hattori
{"title":"Performance and power evaluation of SH-X3 multicore system","authors":"M. Takada, S. Shibahara, K. Hayase, T. Kamei, Y. Yoshida, K. Takada, N. Irie, O. Nishii, T. Hattori","doi":"10.1109/ASSCC.2007.4425678","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425678","url":null,"abstract":"We have developed an embedded processor that supports asymmetric multiple processor (AQMP), symmetric multiple processor (SMP), and an AMP/SMP hybrid system. It contains four SH-X3 cores used to support cache coherency from that obtained using an SH-X2 core. In this paper, we evaluate the following three techniques to improve the processing performance and reduce the power consumption in parallel processing in the processor. The first technique is snoop controller (SiNC) to improve cache coherency performance. The performance overhead by snoop is decreased up to 0.1% when SPLASH-2 is executed. The second technique is detection and resolution of synonym problems so that we may not use the page coloring for page table management. The processes handling time in Linux is reduced by 29.4% compared with the case solved the problem with software. The third technique is the individual core clock frequency and the light sleep mode which is used to maintain the cache coherency even when the cores are stopped, to reduce the power consumption. The energy is decreased by 5.2% and 4.5%, respectively. As a result, the SH-X3 core achieved a performance that has scalability proportional to 0.72-0.93 times the number of cores and a power saving of 4.5-44.0% without increasing the execution time.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism 一种基于脉冲收缩/拉伸机制的低功率宽范围占空比校正器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425730
Poki Chen, Shi-Wei Chen, Juan-Shan Lai
{"title":"A low power wide tange duty cycle corrector based on pulse shrinking/stretching mechanism","authors":"Poki Chen, Shi-Wei Chen, Juan-Shan Lai","doi":"10.1109/ASSCC.2007.4425730","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425730","url":null,"abstract":"A duty cycle corrector based on pulse shrinking/ stretching mechanism is presented. The proposed DCC has been rubricated in a TSMC 0.35mum standard CMOS process. An input duty cycle range of 30%~70% is achieved. The duty cycle error is within plusmn1.0% for the widest frequency operation range of 3MHz~60MHz ever fulfilled which makes the circuit best suited for ultra wide band applications. The chip area is merely 0.3 x 0.2 mm2 and the power consumption is 1. 1mW at 550 MHz.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133971184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
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