发布求助
文献互助 智能选刊 最新文献

2007 IEEE Asian Solid-State Circuits Conference最新文献

筛选
英文 中文
A high S/N ratio and high full well capacity CMOS image sensor with active pixel readout feedback operation 具有主动像素读出反馈操作的高信噪比和高满井容量CMOS图像传感器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425780
Woonghee Lee, N. Akahane, S. Adachi, K. Mizobuchi, S. Sugawa
{"title":"A high S/N ratio and high full well capacity CMOS image sensor with active pixel readout feedback operation","authors":"Woonghee Lee, N. Akahane, S. Adachi, K. Mizobuchi, S. Sugawa","doi":"10.1109/ASSCC.2007.4425780","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425780","url":null,"abstract":"We discuss results of the design and operations of a CMOS image sensor with high S/N ratio while keeping wide dynamic range. Readout gains and input-referred noises of the image sensor are improved by actively using a pixel source follower feedback operation. A 1/4-inch 5.6 mum times 5.6 mum pixel VGA color CMOS image sensor with a lateral overflow integration capacitor in pixel in a 0.18 mum 2P3M CMOS process achieves about 1.7 times the gain compared with the case where the feedback operation is not positively used, resulting in a high input-referred conversion gain exceeded 200 muV/e-, a low input-referred noise below 2 e- without column amplifier and a high full well capacity of about 1.3 times 105 e-.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122728926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Penryn: 45-nm next generation Intel® core™ 2 processor Penryn: 45纳米下一代Intel®core™2处理器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425784
Varghese George, Sanjeev Jahagirdar, Chao Tong, K. Smits, Satish Damaraju, S. Siers, Ves A. Naydenov, T. Khondker, Sanjib Sarkar, Puneet Singh
{"title":"Penryn: 45-nm next generation Intel® core™ 2 processor","authors":"Varghese George, Sanjeev Jahagirdar, Chao Tong, K. Smits, Satish Damaraju, S. Siers, Ves A. Naydenov, T. Khondker, Sanjib Sarkar, Puneet Singh","doi":"10.1109/ASSCC.2007.4425784","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425784","url":null,"abstract":"This paper describes Penryn (codename), Intel–s next generation family of processors implemented in a 45nm High-k metal gate silicon process technology and designed to meet a wide range of power envelopes and market segments. It is a dual-core, 64-bit CPU based on the Core™ microarchitecture with a unified 24-way L2 cache of 6MB. Key new features in Penryn include a Fast Radix- 16 Divider, an SSE4 instruction set, a radically new Power Management state (Deep Power Down) and Enhanced Dynamic Acceleration Technology (EDAT). Active and leakage power reduction techniques are used throughout the design to reduce power consumption while not compromising the scalability requirements. The chip is offered in various package technologies including a MCP version for the Quad-core products.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 77
An NFC transceiver with RF-powered RFID transponder mode 一个NFC收发器与射频供电RFID转发器模式
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425758
Junghyun Cho, Jikon Kim, Jaewhan Kim, Kyungil Lee, Kwang-Duk Aim, Shiho Kim
{"title":"An NFC transceiver with RF-powered RFID transponder mode","authors":"Junghyun Cho, Jikon Kim, Jaewhan Kim, Kyungil Lee, Kwang-Duk Aim, Shiho Kim","doi":"10.1109/ASSCC.2007.4425758","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425758","url":null,"abstract":"A single chip NFC transceiver supporting not only NFC active and passive mode but also 13.56 MHz RFID reader and tag mode was designed and fabricated. The proposed NFC transceiver can operate as a RFID tag even without external power supply thanks to a dual antenna structure for initiator and target. The area increment due to additional target antenna is negligible because the target antenna is constructed by using a shielding layer of initiator antenna.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An SoC based HW/SW co-design architecture for multi-standard audio decoding 基于SoC的多标准音频解码硬件/软件协同设计架构
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425765
Dajiang Zhou, Peilin Liu, Ji Kong, Yunfei Zhang, Bin He, Ning Deng
{"title":"An SoC based HW/SW co-design architecture for multi-standard audio decoding","authors":"Dajiang Zhou, Peilin Liu, Ji Kong, Yunfei Zhang, Bin He, Ning Deng","doi":"10.1109/ASSCC.2007.4425765","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425765","url":null,"abstract":"In this paper, we presented an SoC based HW/SW co-design architecture for multi-standard audio decoding. It is developed to support the audio standards of AAC LC profile, Dolby AC3, Ogg Vorbis, MPEG-1 Layer 3 (MP3) and Windows Media Audio (WMA). A VLSI reconfigurable filterbank based on CORDIC algorithm is developed to accelerate the multi-standard decoding process. We designed and implemented an SoC platform to verify the interbank as an IP core. Experimental result shows that the architecture is able to perform real-time audio decoding at low frequency (typically 10.6MHz for AAC and 11.3 MHz for MP3) and the implementation cost is low (44.3k gates, 34k bytes RAM and 45k bytes data ROM for 5 audio standards). The architecture is also flexible for extending support of new formats and standards.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129403924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
High efficiency CMOS rectifier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs 高效CMOS整流电路，具有自电压抵消和功率调节功能，用于UHF rfid
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425746
K. Kotani, T. Ito
{"title":"High efficiency CMOS rectifier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs","authors":"K. Kotani, T. Ito","doi":"10.1109/ASSCC.2007.4425746","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425746","url":null,"abstract":"High efficiency CMOS rectifier circuit for UHF RFID applications has been developed. The rectifier utilizes self Vth cancellation (SVC) scheme in which threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated by output voltage of the rectifier itself. Very simple circuit configuration and no power dissipation feature of the scheme enable excellent power conversion efficiency (PCE) especially in small RF input power conditions. At higher RF input power conditions, PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. Proposed SVC CMOS rectifier has been fabricated with 0.35 mum CMOS process and the measured performance has been compared with other types of rectifiers. The SVC CMOS rectifier achieves 29% PCE at -9.9 dBm RF input power condition. This PCE is larger than ever reported rectifiers under the condition.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116340397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 156
A low power baseband OFDM receiver IC for fixed WiMAX communication 用于固定WiMAX通信的低功率基带OFDM接收器IC
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425688
Chi-Chie Chang, Chi-Hong Su, Jen-Ming Wu
{"title":"A low power baseband OFDM receiver IC for fixed WiMAX communication","authors":"Chi-Chie Chang, Chi-Hong Su, Jen-Ming Wu","doi":"10.1109/ASSCC.2007.4425688","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425688","url":null,"abstract":"This paper presents the VLSI design and implementation of the baseband inner receiver for IEEE 802.16-2004 (i.e. the fixed WiMAX) OFDM mode. The design consists of low power packet detection, low complexity CORDIC-based carrier frequency compensation, recursive FFT and channel compensation. In the packet detection and carrier frequency compensation, we use sign-bit method, sliding mapping correlator, and the multiplier mapping function to achieve low complexity design. In the FFT design, we use the radix-8 memory-based recursive FFT to achieve small area design. Fabricated in TSMC 0.18 mum technology, the chip occupies 2.4 x 2.4 mm2 area and consumes about 114 mW under 1.8V power supply.1","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127803635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS 采用0.18 μm CMOS片上电感，非接触式10%高效36mW功率输出
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425745
Yuan Yuxiang, Y. Yoshida, T. Kuroda
{"title":"Non-contact 10% efficient 36mW power delivery using on-chip inductor in 0.18-μm CMOS","authors":"Yuan Yuxiang, Y. Yoshida, T. Kuroda","doi":"10.1109/ASSCC.2007.4425745","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425745","url":null,"abstract":"This paper presents design and implementation of an inductive coupling power delivery system between stacked chips in 0.18-mum CMOS process. Two conventional high-power rectifier structures are compared, and a new topology is proposed. With a pair of fully optimized 700 mum times 700 mum on-chip inductors, the test chip achieves 10% peak efficiency and 36 mW power transmission. Compared with previous published chip-to-chip wireless power transmission systems, the received power is 13 times larger.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133636138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 100kHz – 20MHz reconfigurable nauta gm-C biquad low-pass filter in 0.13µm CMOS 100kHz - 20MHz可重构nutagm - c双路低通滤波器，0.13µm CMOS
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425726
P. Crombez, J. Craninckx, M. Steyaert
{"title":"A 100kHz – 20MHz reconfigurable nauta gm-C biquad low-pass filter in 0.13µm CMOS","authors":"P. Crombez, J. Craninckx, M. Steyaert","doi":"10.1109/ASSCC.2007.4425726","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425726","url":null,"abstract":"A fully reconfigurable gm-C biquadratic low-pass filter is presented with a bandwidth tunable over more than two orders of magnitude starting from 100 kHz up to 20 MHz able to cover all common wireless standards. Furthermore, power and performance can be traded thanks to a new switching technique inside Nauta's transconductor that allows changing its transconductance and input capacitance independently. Bandwidth, quality factor, noise level, linearity and common mode suppression arc all programmable over a very wide range. The circuit is realized in a 0.13 mum CMOS technology and consumes between 103 muA (100 kHz) and 11.85 mA (20 MHz) from a 1.2 V supply for a low integrated noise setting around 25 to 35 muVrms and an IIP3 of 10 dBVp giving an SFDR of 68 dB. Extra power can be saved when higher noise levels are allowed. Measurement results confirm flexibility, noise-power scaling and linearity behavior of the biquad architecture.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116610921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Design and implementation of biomedical SoC for implantable cardioverter defibrillators 植入式心律转复除颤器生物医学SoC的设计与实现
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425777
Kilhwan Kim, Unsun Cho, Yunho Jung, Jaeseok Kim
{"title":"Design and implementation of biomedical SoC for implantable cardioverter defibrillators","authors":"Kilhwan Kim, Unsun Cho, Yunho Jung, Jaeseok Kim","doi":"10.1109/ASSCC.2007.4425777","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425777","url":null,"abstract":"In this paper, a biomedical processor was developed for implantable cardioverter defibrillators (ICDs), which delivers appropriate prescriptions for atrial tachycardia and fibrillation to a pacing module of ICD. The diagnosis of heart conditions is determined based on atrial electrograms (EGMs) as sensed from within the heart. The biomedical processor is implemented into a single chip including analog circuit elements. The chip is fabricated in a 0.35 mum CMOS technology, and the chip area is 3.8 times 2.7 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133238062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology 采用SiGe技术的3位20GS/s交错闪存模数转换器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425720
Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger
{"title":"A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology","authors":"Yuan Yao, Xuefeng Yu, Dayu Yang, F. Dai, J. Irwin, R. Jaeger","doi":"10.1109/ASSCC.2007.4425720","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425720","url":null,"abstract":"A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm2. The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信