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4.8GHz CMOS frequency multiplier with subharmonic pulse-injection locking 具有次谐波脉冲注入锁的4.8GHz CMOS倍频器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425699
K. Takano, M. Motoyoshi, M. Fujishima
{"title":"4.8GHz CMOS frequency multiplier with subharmonic pulse-injection locking","authors":"K. Takano, M. Motoyoshi, M. Fujishima","doi":"10.1109/ASSCC.2007.4425699","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425699","url":null,"abstract":"To realize low-power wireless transceivers, it is required to improve the performance of a frequency synthesizer, which is typically used as a frequency multiplier and is composed of a phase-locked loop (PLL). However a general PLL consumes much power and occupies a large area. To improve the frequency multiplier, we propose a pulse-injection-locked frequency multiplier (PILFYM), in which spurious signals are suppressed by using a pulse input signal. An injection-locked oscillator (ILO) in a PILFM was fabricated by a 0.18 mum 1P5M CMOS process. The core size was 10.8 mum x 10 S mum. The power consumption of the ILO is 9.6 muW at 250 MHz, and 1.47 mW at 4.8 GHz. The phase noise is -108 dBc/Hz at 1 MHz offset. For a ten-times frequency multiplier, output phase noise is 10 JB larger than the input phase noise below 10 kHz offset, which is the theoretical limit.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127420600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A 1.5dB NF, 5.8GHz CMOS low-noise amplifier with on-chip matching 具有片上匹配的1.5dB NF, 5.8GHz CMOS低噪声放大器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425741
J. Duster, S. S. Taylor, H. Zhan
{"title":"A 1.5dB NF, 5.8GHz CMOS low-noise amplifier with on-chip matching","authors":"J. Duster, S. S. Taylor, H. Zhan","doi":"10.1109/ASSCC.2007.4425741","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425741","url":null,"abstract":"In this paper we describe the design of an integrated 5.8 GIU low noise amplifier in 90 nm CMOS technology. The design is a tuned cascode LNA with on-chip matching that has a sufficiently low noise figure and high gain to enable high receiver sensitivity. The measured performance is NF=l.SdB, gain=28 dB, IIP3= -5 dBm and Pd=15mV; and NfW.SdB, gain=23 dB, HP3=-17 dBm and Pd=8 mV.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121707192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel design of CAVLC decoder with low power consideration 基于低功耗的CAVLC解码器设计
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425764
T. Tsai, De-Lung Fang
{"title":"A novel design of CAVLC decoder with low power consideration","authors":"T. Tsai, De-Lung Fang","doi":"10.1109/ASSCC.2007.4425764","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425764","url":null,"abstract":"This paper proposes a novel architecture and its VLSI design for MPEG-4 AVC/H.264 CAVLC decoding. In order to improve throughput of CAVLC decoder, we propose two new methods, which are called MLD (Multi-Level Decoding) and NZS (Non Zero Skip for run_before decoding). By performing parallel operation on level decoder, MLD can decode two levels in one cycle at most situations, and NZS can produce several run_befores in the same cycle. These two methods have the advantages of low complexity and regularity design. According to the evaluation, our design only needs 137 cycles in average for one macroblock decoding. Moreover, the proposed CAVLC decoder can run at 33.5 MHz to meet the real time requirement for H.264 video decoding on 1920 times1088 resolution. Compared with the previous designs, it can reduce around 29.1% to 71.5% on operation frequency for the same requirement, but not increase the gate count so much. With an aid on a lower operation frequency, it will be suitable for a low power application.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128116899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A CMOS linear-in-dB high-linearity variable-gain amplifier for UWB receivers 一种用于UWB接收机的CMOS线性- db高线性变增益放大器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425742
Chan Tat Fu, H. Luong
{"title":"A CMOS linear-in-dB high-linearity variable-gain amplifier for UWB receivers","authors":"Chan Tat Fu, H. Luong","doi":"10.1109/ASSCC.2007.4425742","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425742","url":null,"abstract":"This paper presents a CMOS linear-in-dB variable gain amplifier (VGA) that provides a variable gain range over 90 dB with 3 dB bandwidth greater than 400 MHz at 54 dB gain. The maximum output 1 dB compression point is 9 dBm. Maximum gain error is +/-2 dB. It consumes total 22 mW with 1.8 V supply, including control circuit. This VGA is fabricated in TSMC 0.18 um CMOS process and demonstrate the performance of the proposed dB-linear VGA.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A quad 1–10Gb/s serial transceiver in 90nm CMOS 90nm CMOS的四路1-10Gb /s串行收发器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425753
Han Bi, Yehui Sun, Kai Lei, Zixin Wu, Xinqing Chen, Song Gao, Junning Wang, Yongyi Wu, Hui Wang
{"title":"A quad 1–10Gb/s serial transceiver in 90nm CMOS","authors":"Han Bi, Yehui Sun, Kai Lei, Zixin Wu, Xinqing Chen, Song Gao, Junning Wang, Yongyi Wu, Hui Wang","doi":"10.1109/ASSCC.2007.4425753","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425753","url":null,"abstract":"A quad 1-10 Gb/s serial transceiver in 90 nm digital CMOS technology is presented in this paper. A combination of transmitter pre-emphasis and receiver equalization is used. It can be used for different data rates and short-reach/long-reach applications with low overhead in area and power consumption. It is able to run across a 60-inch FR4 PCB trace with BER<10-12 at 3.125 Gb/s while consuming 70 mW/channel. At 10 Gb/s, it consumes 98 mW/channel to run across a 10-inch FR4 PCB trace and 90mW/channcl to run across a 4-inch FR4 PCB trace. Its die area is 1.6 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130893069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Value creation in SOC/MCU applications by embedded non-volatile memory evolutions 通过嵌入式非易失性存储器的进化在SOC/MCU应用中创造价值
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425790
M. Hatanaka, H. Hidaka
{"title":"Value creation in SOC/MCU applications by embedded non-volatile memory evolutions","authors":"M. Hatanaka, H. Hidaka","doi":"10.1109/ASSCC.2007.4425790","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425790","url":null,"abstract":"Flash-MCU, micro-controller with embedded flash memory storage (eFlash), has seen a tremendous up-surge in real-time control application markets, with assumed 15-20% CAGR. The programmable code storage provided by eFlash contributes to production cost reduction and real-time adaptive control applications, realizing a value innovation with remarkable cost/value advantage. The diversified advanced eFlash technology for converging flash-MCU products challenges new market drivers like automotive and smart-IC cards. Current status and future directions of flash-MCU with evolution of LSI by programmability functions are also reviewed.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131683544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 10-bit binary-weighted DAC with digital background LMS calibration 一个10位二进制加权DAC与数字背景LMS校准
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425703
D. Shen, Yuan-Chun Lai, Tai-Cheng Lee
{"title":"A 10-bit binary-weighted DAC with digital background LMS calibration","authors":"D. Shen, Yuan-Chun Lai, Tai-Cheng Lee","doi":"10.1109/ASSCC.2007.4425703","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425703","url":null,"abstract":"A 10-bit binary-weighted DAC utilizes identical transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm2 in a 0.18-mum CMOS technology and consumes 27 mW from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132173736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme 一个4mb的MRAM宏，包括共享写选择晶体管单元，并使用泄漏复制读取方案
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425770
R. Nebashi, N. Sakimura, T. Sugibayashi, N. Kasai
{"title":"A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme","authors":"R. Nebashi, N. Sakimura, T. Sugibayashi, N. Kasai","doi":"10.1109/ASSCC.2007.4425770","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425770","url":null,"abstract":"We propose an MRAM macro architecture for SoCs to reduce their area size. The .shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology', which enables the same fast access time as and with smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-mum CMOS process and a 0.24-mum MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 hits of data. Area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129017183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Implementation of Memory-Centric NoC for 81.6 GOPS object recognition processor 81.6 GOPS目标识别处理器的内存中心NoC实现
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425679
Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, H. Yoo
{"title":"Implementation of Memory-Centric NoC for 81.6 GOPS object recognition processor","authors":"Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, H. Yoo","doi":"10.1109/ASSCC.2007.4425679","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425679","url":null,"abstract":"An 81.6 GOPS object recognition processor based on memory-centric NoC (MC-NoC) is implemented in a 0.18-mum CMOS technology. The MC-NoC facilitates data transactions among 10 SIMD processing elements (PEs) by exploiting 8 visual image processing (VIP) memories. The 10 PEs implement special SIMD instructions to perform Gaussian filtering at 16 GOPS. The 8 VIP memories provide one cycle local maximum pixels search operation performing 65.6 GOPS. The chip dissipates 1.4 W at 200 MHz operating frequency.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132089847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A high-speed low-complexity two-parallel radix-24 FFT/IFFT processor for UWB applications 一种用于超宽带应用的高速低复杂度双并行基数24 FFT/IFFT处理器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425686
Hanho Lee, Minhyeok Shin
{"title":"A high-speed low-complexity two-parallel radix-24 FFT/IFFT processor for UWB applications","authors":"Hanho Lee, Minhyeok Shin","doi":"10.1109/ASSCC.2007.4425686","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425686","url":null,"abstract":"This paper presents a high-speed, low-complexity two data-path 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed FFT processor uses a method for compensating the truncation error of fixed-with Booth multipliers with Dadda reduction network, which keep the input and output the 8-bit width. This method leads to reduction of truncation errors compared with direct-truncated multipliers. It provides lower hardware complexity and high throughput with almost same SQNR compared with direct-truncated Booth multipliers. The proposed FFT/IFFT processor has been designed and implemented with 0.18-mum CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122690476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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