A novel design of CAVLC decoder with low power consideration

Abstract

This paper proposes a novel architecture and its VLSI design for MPEG-4 AVC/H.264 CAVLC decoding. In order to improve throughput of CAVLC decoder, we propose two new methods, which are called MLD (Multi-Level Decoding) and NZS (Non Zero Skip for run_before decoding). By performing parallel operation on level decoder, MLD can decode two levels in one cycle at most situations, and NZS can produce several run_befores in the same cycle. These two methods have the advantages of low complexity and regularity design. According to the evaluation, our design only needs 137 cycles in average for one macroblock decoding. Moreover, the proposed CAVLC decoder can run at 33.5 MHz to meet the real time requirement for H.264 video decoding on 1920 times1088 resolution. Compared with the previous designs, it can reduce around 29.1% to 71.5% on operation frequency for the same requirement, but not increase the gate count so much. With an aid on a lower operation frequency, it will be suitable for a low power application.