发布求助
文献互助 智能选刊 最新文献

2007 IEEE Asian Solid-State Circuits Conference最新文献

筛选
英文 中文
A 65nm Pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure 一种65nm纯CMOS一次性可编程存储器，采用在矩阵结构中实现的双端口防熔丝单元
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425768
K. Matsufuji, T. Namekawa, H. Nakano, H. Ito, O. Wada, N. Otsuka
{"title":"A 65nm Pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure","authors":"K. Matsufuji, T. Namekawa, H. Nakano, H. Ito, O. Wada, N. Otsuka","doi":"10.1109/ASSCC.2007.4425768","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425768","url":null,"abstract":"A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem and realizes pseudo \"1\" read test. An 8 Kbit macro is developed utilizing a 65 nm pure CMOS logic technology. The cell area and the macro size are 15.3 mum2 and 0.244 mm2, respectively.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A reconfigurable microcomputer system with PA3 (Programmable Autonomous Address-control-memory Architecture) 具有PA3(可编程自治地址控制存储器结构)的可重构微机系统
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425712
Y. Kawamura
{"title":"A reconfigurable microcomputer system with PA3 (Programmable Autonomous Address-control-memory Architecture)","authors":"Y. Kawamura","doi":"10.1109/ASSCC.2007.4425712","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425712","url":null,"abstract":"A programmable autonomous address-control-memory architecture (PA3) which supports memory based reconfigurable microcomputer (user structured microcomputer) is proposed. The PA3 provides finite autonomous device and executes the state transition control without CPU. The PA3 can be directly accessed as memory and support logic operation circuit of counter, and PWM, etc. When the logical function is mounted on silicon using the PA3, there is no need to relocate and rewire like FPGA. Each logic function module is achieved by loading the library which include logic function and wiring information. The performance depends on the characteristic of SRAM. The Standards bus interface of PA3 also supports both memory and peripheral buses in a microcomputer. The PA3 modeling and evaluation of the basic logical operation / function modules have been simulated.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120964305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ultra low power IC for an autonomous mm3-sized microrobot 一种用于3毫米大小的自主微型机器人的超低功耗集成电路
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425681
R. Casanova, Á. Diéguez, A. Sanuy, A. Arbat, O. Alonso, J. Canals, J. Samitier
{"title":"An ultra low power IC for an autonomous mm3-sized microrobot","authors":"R. Casanova, Á. Diéguez, A. Sanuy, A. Arbat, O. Alonso, J. Canals, J. Samitier","doi":"10.1109/ASSCC.2007.4425681","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425681","url":null,"abstract":"This paper is focused on the main issues of designing a SoC for a completely autonomous mm3-sized microrobot. It is described how all the electronics are included in a unique chip, the special requirements in the assembly process and how the hard constraints in power consumption are managed. Power in the robot is delivered by solar cells mounted on top and two supercapacitors which act as batteries. The maximum available energy for the SoC is 400 muW for driving the robot actuators and 1 mW for data processing. The special architecture of the SoC and power awareness are required to manage the very low available power.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 500-MHz ΣΔ phase-interpolation direct digital synthesizer 一个500-MHz ΣΔ相位插值直接数字合成器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425728
T. Finateu, I. Miro-Panadès, F. Boissieres, J. Bégueret, Y. Deval, D. Belot, F. Badets
{"title":"A 500-MHz ΣΔ phase-interpolation direct digital synthesizer","authors":"T. Finateu, I. Miro-Panadès, F. Boissieres, J. Bégueret, Y. Deval, D. Belot, F. Badets","doi":"10.1109/ASSCC.2007.4425728","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425728","url":null,"abstract":"A SigmaDelta phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The SigmaDelta enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroclectronics technology. The power consumption is about 29 mVV without buffers under 1.2 V for a 500-MHz operating frequency.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A low-power current-mode transceiver with simultaneous data and clock transmission at 625Mb/s, 3 mW in 1.5 V for mobile applications 一种低功耗电流模式收发器，同时具有625Mb/s的数据和时钟传输速度，1.5 V下3 mW，适用于移动应用
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425755
T. Ogino, T. Yoshikawa, M. Nagata
{"title":"A low-power current-mode transceiver with simultaneous data and clock transmission at 625Mb/s, 3 mW in 1.5 V for mobile applications","authors":"T. Ogino, T. Yoshikawa, M. Nagata","doi":"10.1109/ASSCC.2007.4425755","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425755","url":null,"abstract":"A current-mode data transceiver for mobile applications is described. This transceiver has a multi-level current transmitter with simple clock recovery and a low-input impedance receiver, and realizes low-voltage swing (about 20 mV) with 150-300 muA drive current at 625 Mbps by differential manner. The transceiver operates with a 1.5-V single power supply, and consumes 3 mV including transmitter and receiver when simultaneous data and clock transmission at 625 Mbps is achieved through a single differential I/O connecting the transmitter and receiver pair.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock 一个180-Mb/s至3.2 gb /s，连续速率，快速锁定话单，不使用外部参考时钟
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425751
Moon-Sang Hwang, Sangyoon Lee, Jeong-Kyoum Kim, Suhwan Kim, D. Jeong
{"title":"A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock","authors":"Moon-Sang Hwang, Sangyoon Lee, Jeong-Kyoum Kim, Suhwan Kim, D. Jeong","doi":"10.1109/ASSCC.2007.4425751","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425751","url":null,"abstract":"A referenceless, continuous-rate, fast-locking CDR with an operating range of 180 Mb/s to 3.2 Gb/s is presented. The harmonic lock property of a rotational frequency detector and the maximum run-length limit of 8B10B encoded data are utilized to detect a harmonic lock and to accelerate acquisition process. A separate VCO control scheme is introduced to stabilize the loop with a modest amount of on-chip capacitance.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A novel compression method for wireless image sensor node 一种新的无线图像传感器节点压缩方法
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425761
Xinkai Chen, Hanjun Jiang, Xiao Wen Li, Zhihua Wang
{"title":"A novel compression method for wireless image sensor node","authors":"Xinkai Chen, Hanjun Jiang, Xiao Wen Li, Zhihua Wang","doi":"10.1109/ASSCC.2007.4425761","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425761","url":null,"abstract":"This paper presents the design of a novel compression method for wireless image sensor node. In order to meet the requirement of the wireless image sensor node, a dedicated filtering procedure is developed for raw Bayer CFA pattern. JPEG-LS encoder follows the filtering procedure to compress the data. The parallel and pipeline structure are chosen for the purpose of high throughput and real-time operation. The compression method is implemented using UMC 0.18 mum technology. The test results shown that the image with VGA (640times480) resolution and frame rate 15 fps can be achieved with the same clock frequency with the CMOS image sensor.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 10Gb/s burst-mode transimpedance amplifier in 0.13μm CMOS 基于0.13μm CMOS的10Gb/s突发模式跨阻放大器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425715
Hong-Lin Chu, Shen-Iuan Liu
{"title":"A 10Gb/s burst-mode transimpedance amplifier in 0.13μm CMOS","authors":"Hong-Lin Chu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2007.4425715","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425715","url":null,"abstract":"This paper presents a 10 Gb/s burst-mode transimpedance amplifier (BMTIA), which has been fabricated in a 0.13 mum CMOS process. For the burst-mode receivers in passive optical networks (PONs), the preamplifier has to receive the burst-mode data packages with different amplitudes and provides a short settling time which is required for high data transmission efficiency. In this paper, a 10 Gb/s BMTIA is presented to achieve a wide dynamic range of 42.5 dB and fast settling time within Ins. It dissipates 7.2 mW excluding output buffer from a single 1.2 V supply voltage.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL 0.67μW/MHz, 5ps抖动，4个锁定周期，65nm ADDLL
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425690
Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang
{"title":"A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL","authors":"Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang","doi":"10.1109/ASSCC.2007.4425690","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425690","url":null,"abstract":"This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A capacitor-free fast-transient-response LDO with dual-loop controlled paths 具有双环控制路径的无电容快速瞬态响应LDO
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425706
Jiann-Jong Chen, F. Yang, Che-Min Kung, Bao-Peng Lai, Yuh-Shyan Hwang
{"title":"A capacitor-free fast-transient-response LDO with dual-loop controlled paths","authors":"Jiann-Jong Chen, F. Yang, Che-Min Kung, Bao-Peng Lai, Yuh-Shyan Hwang","doi":"10.1109/ASSCC.2007.4425706","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425706","url":null,"abstract":"A capacitor-free fast-transient-response low-dropout voltage regulator (LDO) with dual-loop controlled paths is presented in this paper. This technique can make the transient response to be faster than other LDOs with traditional controlled loop. Especially, the performance of settling time of proposed LDO is excellent without off-chip capacitors. With 1.5 V power supply voltage, the output voltage is designed as 1.2V. The prototype of the LDO is fabricated with TSMC 0.35-mum DPQM CMOS processes. The active area is only 360 mum times 345 mum.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信