0.67μW/MHz, 5ps抖动，4个锁定周期，65nm ADDLL

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI:10.1109/ASSCC.2007.4425690

Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang

{"title":"0.67μW/MHz, 5ps抖动，4个锁定周期，65nm ADDLL","authors":"Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang","doi":"10.1109/ASSCC.2007.4425690","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL\",\"authors\":\"Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang\",\"doi\":\"10.1109/ASSCC.2007.4425690\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425690\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

本文提出了一个1.0 V 150-550 MHz的65 nm ADDLL的设计，采用了一种新颖的粗精结构和差分电路技术。当工作在550mhz时，该纳米ADDLL在最短的4个锁定周期内实现了5ps的峰间抖动，而功耗仅为0.67 muW/MHz，与现有最节能的ADDLL相比降低了约72%。

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A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL

This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.

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来源期刊

2007 IEEE Asian Solid-State Circuits Conference

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