{"title":"一个10位二进制加权DAC与数字背景LMS校准","authors":"D. Shen, Yuan-Chun Lai, Tai-Cheng Lee","doi":"10.1109/ASSCC.2007.4425703","DOIUrl":null,"url":null,"abstract":"A 10-bit binary-weighted DAC utilizes identical transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm2 in a 0.18-mum CMOS technology and consumes 27 mW from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"416 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 10-bit binary-weighted DAC with digital background LMS calibration\",\"authors\":\"D. Shen, Yuan-Chun Lai, Tai-Cheng Lee\",\"doi\":\"10.1109/ASSCC.2007.4425703\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit binary-weighted DAC utilizes identical transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm2 in a 0.18-mum CMOS technology and consumes 27 mW from a 1.8-V supply.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"416 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425703\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425703","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10-bit binary-weighted DAC with digital background LMS calibration
A 10-bit binary-weighted DAC utilizes identical transistors with different overdrive voltages to achieve small area and high speed. Employing LMS calibration, the proposed current-steering DAC can be digitally calibrated in the background. The measured SFDR of the output signal at 61 kHz can be improved by 19 dB at 1 GS/s. The 10-bit DAC occupies 0.2 mm2 in a 0.18-mum CMOS technology and consumes 27 mW from a 1.8-V supply.
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