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A wideband fractional-N frequency synthesizer with linearized coarse-tuned VCO for UHF/VHF mobile broadcasting tuners 用于UHF/VHF移动广播调谐器的带线性化粗调谐压控振荡器的宽带分数n频率合成器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425725
Jaewook Shin, Jongsik Kim, Seungsoo Kim, Jeongki Choi, Nam-Keal Kim, Y. Eo, Hyunchol Shin
{"title":"A wideband fractional-N frequency synthesizer with linearized coarse-tuned VCO for UHF/VHF mobile broadcasting tuners","authors":"Jaewook Shin, Jongsik Kim, Seungsoo Kim, Jeongki Choi, Nam-Keal Kim, Y. Eo, Hyunchol Shin","doi":"10.1109/ASSCC.2007.4425725","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425725","url":null,"abstract":"A fractional-N frequency synthesizer with a fractional bandwidth of 67% for UHF/VHF-band mobile broadcasting tuners is presented. A novel linearized coarse tuned VCO with a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth. The proposed technique successfully reduces the variation of KVCO and per-code frequency step by 2.7 and 2.1 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) structure is employed for high speed operation, low power consumption, and small silicon area. Implemented in 0.18-mum CMOS, the PLL covers 154 ~ 303 MHz (VHF) and 462 ~ 911 MHz (UHF) with a single VCO. The integrated phase noise is 0.807 and 0.910 degree for the integer-N and fractional-N modes, respectively, at 827.5-MHz output frequency. The in-band noise at 1 kHz offset is -95 dBc/Hz in the integer-N mode and degraded only by 3.8 dB in the fractional-N mode.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114774728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 622Mb/s BPSK demodulator with mixed-mode demodulation scheme 采用混合模式解调方案的622Mb/s BPSK解调器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425687
Duho Kim, Y. Seo, Hyunchin Kim, W. Choi
{"title":"A 622Mb/s BPSK demodulator with mixed-mode demodulation scheme","authors":"Duho Kim, Y. Seo, Hyunchin Kim, W. Choi","doi":"10.1109/ASSCC.2007.4425687","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425687","url":null,"abstract":"A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications based on cable TV lines. A prototype chip is realized that can demodulate up to 622 Mb/s data at 1.4 GHz carrier frequency.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding 用于MPEG-4视频编码的片上网络的功耗
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425713
D. Milojevic, L. Montperrus, D. Verkest
{"title":"Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding","authors":"D. Milojevic, L. Montperrus, D. Verkest","doi":"10.1109/ASSCC.2007.4425713","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425713","url":null,"abstract":"In this paper we present a multi-processor system-on-chip (MPSoC) platform with six computational and four memory nodes interconnected with Arteris network-on-chip (NoC). The platform is dedicated for real-time video encoding applications for high resolution images (HDTV) and frame rates of up to 30 fps. Extensive experiments established the power dissipation models of all individual NoC components, i.e. network interfaces, routers and wires. Based on these power models and the NoC topology we built the power model of the complete NoC. Finally we derive the power dissipation of the NoC for MPEG4 simple profile encoder. The results show that depending on the image resolution the power dissipation of the communication infrastructure vary between 15 and 22 mW, which is comparable with the state of the art dedicated low-power implementations.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116923907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 0.026mm2 capacitance-to-digital converter for biotelemetry applications using a charge redistribution technique 0.026mm2电容-数字转换器，用于生物遥测应用，采用电荷再分配技术
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425776
Kota Tanaka, Y. Kuramochi, T. Kurashina, K. Okada, Akira Matsuzawa
{"title":"A 0.026mm2 capacitance-to-digital converter for biotelemetry applications using a charge redistribution technique","authors":"Kota Tanaka, Y. Kuramochi, T. Kurashina, K. Okada, Akira Matsuzawa","doi":"10.1109/ASSCC.2007.4425776","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425776","url":null,"abstract":"This paper proposes a direct capacitance-to-digital converter (CDC) for biotelemetry applications. The proposed circuit is based on a charge redistribution technique using a capacitive sensor and a ranging capacitor array. The circuit does not require accurate reference voltages, so it is robust for fluctuation of supply voltage. Output-code range can be dynamically zoomed in arbitrary capacitance range of sensor output by using the ranging capacitor array. An 8-bit converter with an active area of 0.026 mm2, consuming 0.9 nJ per sample, is demonstrated. The proposed circuit maintains its performance even in the condition of 28% fluctuations in supply voltage. Measurement results of the readout circuit are also demonstrated, which shows that the proposed circuit can work well in the presence of large parasitic capacitances.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129568744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Analog design challenges in nanometer CMOS technologies 纳米CMOS技术中的模拟设计挑战
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425792
W. Sansen
{"title":"Analog design challenges in nanometer CMOS technologies","authors":"W. Sansen","doi":"10.1109/ASSCC.2007.4425792","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425792","url":null,"abstract":"This paper provides a review of all important effects in nm CMOS technologies, with 1 volt supply voltages. They are the reduction of the transconduction, the increase of the gate current, the noise and the mismatch. It is followed by an overview of amplifiers/filters configurations with both Gate and Bulk drives. A large number of sub-1 volt circuits are then provided for sake of illustration, including sigma-delta modulators.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121122978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A 3–10 GHz full-band single VCO agile switching frequency generator for MB-OFDM UWB 用于MB-OFDM UWB的3 - 10ghz全频段单压控振荡器敏捷开关频率发生器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425735
Chao-Shiun Wang, Wei-Chang Li, Chomg-Kuang Wang, Homg-Yuan Shih, Tzu-Yi Yang
{"title":"A 3–10 GHz full-band single VCO agile switching frequency generator for MB-OFDM UWB","authors":"Chao-Shiun Wang, Wei-Chang Li, Chomg-Kuang Wang, Homg-Yuan Shih, Tzu-Yi Yang","doi":"10.1109/ASSCC.2007.4425735","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425735","url":null,"abstract":"This paper presents an agile switching frequency generator with a single voltage controlled oscillator (VCO) covering all the 14 bands for MB-OFDM UWB system. The proposed architecture with the group selection mixers is designed to simplify the synthesizer implementation for optimizing the system power consumption and harmonic sideband spurious suppression. This frequency generator, which consists of a series of dividers, quadrature counterbalance single sideband mixers and output buffers, achieves an agile switching lime of 7 ns and the unwanted sidebands of less than 35 dBc. The circuit occupies an active area of 1.8x1.6 mm2 in a 0.13 mum mixed mode CMOS technology. The overall system draws a current consumption of 49 mA from a 1.2 V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121814426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 7mA-1.8V, 2MHz GFSK analog demodulator with 1Mbps data rate 7mA-1.8V, 2MHz GFSK模拟解调器，数据速率1Mbps
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425737
Jinke Yao, B. Chi, Zhihua Wang
{"title":"A 7mA-1.8V, 2MHz GFSK analog demodulator with 1Mbps data rate","authors":"Jinke Yao, B. Chi, Zhihua Wang","doi":"10.1109/ASSCC.2007.4425737","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425737","url":null,"abstract":"A 7 mA-1.8 V, 2 MHz GFSK analog demodulator with 1 Mbps data rate for the short-distance wireless communication systems is presented. The demodulator includes a 5-order Butterworth pre-filter with 4 MHz bandwidth, a 7-stage limiter, a quadrature frequency discriminator with 4-order Bessel phase-shift network, a 4-order Butterworth post-filter with 800 kHz bandwidth and a differentiator-based bit discriminator. Three filters share a same PLL-based automatic tuning network to lower down the power consumption. The system optimization is carried out to select the coupling scheme between various blocks, the gain assign scheme, the bandwidth plan, as well as the order of the Bessel low pass network as the 90deg phase shifter. All the blocks are designed with the target of low power, high carrier frequency offset and high data rate at the 1.8 V power supply. The GFSK analog demodulator has been implemented in 0.18 mum CMOS. The measured results show that the demodulator could directly restore the digital data from a 2 MHz GFSK signals with 1 Mbps data rate and plusmn160 KHz maximum frequency deviation. The analog demodulator has a sensitivity of -53 dBm, and could undertake a high carrier frequency offset (from 1.3 MHz to 2.7 MHz). It draws 7 mA current from a power supply of 1.8 V.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116554577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer 3.125 Gbps CMOS全集成光接收机，具有自适应模拟均衡器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425714
Wei-Zen Chen, Shih-Hao Huang, Guo-Wei Wu, Chuanchang Liu, Yang-Tung Huang, C. Chin, Wen-Hsu Chang, Y. Juang
{"title":"A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer","authors":"Wei-Zen Chen, Shih-Hao Huang, Guo-Wei Wu, Chuanchang Liu, Yang-Tung Huang, C. Chin, Wen-Hsu Chang, Y. Juang","doi":"10.1109/ASSCC.2007.4425714","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425714","url":null,"abstract":"This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 inVpp to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SiVIL) detector and adaptive analog equalizer. Implemented in a 0.18 mum CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114310145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
An Adaptive ΣΔ modulator for multi-standard hand-held wireless devices 用于多标准手持无线设备的自适应ΣΔ调制器
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425773
A. Morgado, R. del Río, J. M. de la Rosa
{"title":"An Adaptive ΣΔ modulator for multi-standard hand-held wireless devices","authors":"A. Morgado, R. del Río, J. M. de la Rosa","doi":"10.1109/ASSCC.2007.4425773","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425773","url":null,"abstract":"This paper describes the design and experimental characterization of a 130-nm CMOS cascade SigmaDelta modulator intended for multi-standard wireless telecom systems. Both architectural-and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt its performance to different standard specifications with optimized power dissipation. Measurements show a correct operation for GSM/Blue-tooth/WCDMA standards, featuring a dynamic range of 86.7/81.0/63.3dB and a peak signal-to-(noise+distortion) ratio of 74.0/68.4/52.8 dB within 200kHz/1MHz/4MHz, respectively. The power consumption is 25.2/25.0/44.5 mW, of which 11.0/10.5/24.8 are due to the analog part of the circuit+1.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114799188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Dynamic Voltage and Frequency Scaling (DVFS) scheme for multi-domains power management 多域电源管理的动态电压和频率缩放(DVFS)方案
2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI: 10.1109/ASSCC.2007.4425705
Jeabin Lee, Byeong-Gyu Nam, H. Yoo
{"title":"Dynamic Voltage and Frequency Scaling (DVFS) scheme for multi-domains power management","authors":"Jeabin Lee, Byeong-Gyu Nam, H. Yoo","doi":"10.1109/ASSCC.2007.4425705","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425705","url":null,"abstract":"The power of 3 different power domains is managed by continuous co-locking of voltage and clock, dynamically varying clock frequency and supply voltage level from 90 MHz to 200 MHz and from 1.0 V to 1.8 V, respectively. A test 3D-graphics SoC is divided into 3 power domains and their power are managed separately. The workload of each domain is the control parameter to each power management unit (PMU). It takes 0.45 mm2 with 0.18 um CMOS process and consumes 5 mW. Total SoC takes 17.2 mm2 and consumes 52.4 mW at full operation with triple domains power management.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124762774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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