纳米CMOS技术中的模拟设计挑战

2007 IEEE Asian Solid-State Circuits Conference Pub Date : 2007-11-01 DOI:10.1109/ASSCC.2007.4425792

W. Sansen

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引用次数: 46

摘要

本文综述了在1伏电源电压下纳米CMOS技术的所有重要影响。它们是传导减小、栅极电流增大、噪声和失配。其次是放大器/滤波器配置与门和批量驱动器的概述。为了便于说明，这里提供了大量的1伏以下的电路，包括σ - δ调制器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analog design challenges in nanometer CMOS technologies

This paper provides a review of all important effects in nm CMOS technologies, with 1 volt supply voltages. They are the reduction of the transconduction, the increase of the gate current, the noise and the mismatch. It is followed by an overview of amplifiers/filters configurations with both Gate and Bulk drives. A large number of sub-1 volt circuits are then provided for sake of illustration, including sigma-delta modulators.

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2007 IEEE Asian Solid-State Circuits Conference

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