A 7mA-1.8V, 2MHz GFSK analog demodulator with 1Mbps data rate

A 7 mA-1.8 V, 2 MHz GFSK analog demodulator with 1 Mbps data rate for the short-distance wireless communication systems is presented. The demodulator includes a 5-order Butterworth pre-filter with 4 MHz bandwidth, a 7-stage limiter, a quadrature frequency discriminator with 4-order Bessel phase-shift network, a 4-order Butterworth post-filter with 800 kHz bandwidth and a differentiator-based bit discriminator. Three filters share a same PLL-based automatic tuning network to lower down the power consumption. The system optimization is carried out to select the coupling scheme between various blocks, the gain assign scheme, the bandwidth plan, as well as the order of the Bessel low pass network as the 90deg phase shifter. All the blocks are designed with the target of low power, high carrier frequency offset and high data rate at the 1.8 V power supply. The GFSK analog demodulator has been implemented in 0.18 mum CMOS. The measured results show that the demodulator could directly restore the digital data from a 2 MHz GFSK signals with 1 Mbps data rate and plusmn160 KHz maximum frequency deviation. The analog demodulator has a sensitivity of -53 dBm, and could undertake a high carrier frequency offset (from 1.3 MHz to 2.7 MHz). It draws 7 mA current from a power supply of 1.8 V.