{"title":"A CMOS wide-band low-noise amplifier with balun-based noise-canceling technique","authors":"Youchun Liao, Zhangwen Tang, Hao Min","doi":"10.1109/ASSCC.2007.4425739","DOIUrl":null,"url":null,"abstract":"A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425739","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
A differential high linearity low-noise amplifier (LNA) based on a capacitor-cross-coupled topology is presented in this paper. An off-chip balun is used for providing DC-bias and canceling the channel thermal noise of the transconductance MOS transistors. The LNA uses NMOS load and provides an extra signal feed-forward and noise-canceling path. Analysis shows that the noise contribution of the transconductance MOST is only gamma/20 and the noise figure (NF) of the proposed LNA is 1 + 0.2gamma. The chip is implemented in a 0.18-mum MMRF CMOS process. Measured results show that in 50 M-860 MHz frequency range, the LNA achieved 15 dB gain, 2.5 dB NF, 8.3 dBm IIP3 and consumes only 4 mA current from a 1.8-V supply.