Backgate bias accelerator for 10ns-order sleep-to-active modes transition time

Abstract

Backgate biasing is a promising technique for high-speed systems. Leakage can be reduced during standby periods by reverse bias while adequate bias in active mode can balance process and temperature variations. This technique introduces no delay penalty in active mode but slow wake up time results in system performance degradation. In this paper, a backgate bias accelerator achieving 24 ns/V sleep-to-active mode transition rate is demonstrated in a 90 nm CMOS technology. The circuit performs auto-calibration of the transition time as a function of the sleep and active mode backgate bias voltages. Those can therefore be tuned on-chip according to process variations and/or operating conditions. The accelerator occupies less than 2.5% of the total chip area, consumes 600 muW during the transitions and doesn't add any bias current during active and sleep modes.