Jung-Won Han, Boo-Young Choi, Kang-Yeob Park, W. Oh, Sung Min Park
{"title":"2.5Gb/s防静电双通道光收发器阵列","authors":"Jung-Won Han, Boo-Young Choi, Kang-Yeob Park, W. Oh, Sung Min Park","doi":"10.1109/ASSCC.2007.4425754","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18 mum CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5 Gb/s, equipped with the APC (5-15 mA) and AMC (4-20 mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87 dBOmega transimpedance gain, 1.4 GHz bandwidth for 2 pF input parasitic capacitance, -18 dBm sensitivity for 10-12 BER, and less than -20 dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500 mW.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A 2.5Gb/s ESD-protected dual-channel optical transceiver array\",\"authors\":\"Jung-Won Han, Boo-Young Choi, Kang-Yeob Park, W. Oh, Sung Min Park\",\"doi\":\"10.1109/ASSCC.2007.4425754\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18 mum CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5 Gb/s, equipped with the APC (5-15 mA) and AMC (4-20 mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87 dBOmega transimpedance gain, 1.4 GHz bandwidth for 2 pF input parasitic capacitance, -18 dBm sensitivity for 10-12 BER, and less than -20 dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500 mW.\",\"PeriodicalId\":186095,\"journal\":{\"name\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"2016 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2007.4425754\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425754","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.5Gb/s ESD-protected dual-channel optical transceiver array
This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18 mum CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5 Gb/s, equipped with the APC (5-15 mA) and AMC (4-20 mApp) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87 dBOmega transimpedance gain, 1.4 GHz bandwidth for 2 pF input parasitic capacitance, -18 dBm sensitivity for 10-12 BER, and less than -20 dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500 mW.