A 480-MHz to 1-GHz sub-picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13-µm CMOS

Joonhee Lee, Kyunglok Kim, Junghyup Lee, Taekwang Jang, Seonghwan Cho
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引用次数: 27

Abstract

In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. To achieve low jitter, the clock generator uses an LC-VCO with S-bit switched tuning scheme. The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small variation in the loop bandwidth. The capacitor array of the the VCO is controlled by a novel AFC technique that performs binary search for fast calibration and fine search to select an optimum tuning curve. A prototype chip implemented in 0.13-mum CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 1.2 V supply. The measured tins jitter and calibration time of the proposed clock generator are 940 fs at 600 MM/, and 350 ns, respectively. These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator.
一个480-MHz至1 ghz的亚皮秒时钟发生器,在0.13µm CMOS中具有快速准确的自动频率校准
本文提出了一种超低抖动时钟发生器,它采用了一种新颖的自动频率校准技术。为了实现低抖动,时钟发生器采用LC-VCO和s位开关调谐方案。时钟输出取自一个多模分频器的输出,它增加了输出频率范围,环路带宽变化很小。采用一种新颖的AFC技术对VCO的电容阵列进行控制,该技术通过二叉搜索进行快速校准和精细搜索以选择最佳调谐曲线。在0.13 μ m CMOS工艺中实现的原型芯片在1.2 V电源消耗22 mW的情况下实现480 MHz至1 GHz的输出频率。时钟发生器在600 MM/秒时的测量抖动和校准时间分别为940 fs和350 ns。这些数字是在时钟发生器中报告的最快校准时间和最低抖动之一。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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