K. Mizumoto, T. Tanizaki, S. Kobayashi, M. Nakajima, T. Gyohten, H. Yamasaki, H. Noda, M. Higashida, Y. Okuno, K. Arimoto
{"title":"A multi matrix-processor core architecture for real-time image processing SoC","authors":"K. Mizumoto, T. Tanizaki, S. Kobayashi, M. Nakajima, T. Gyohten, H. Yamasaki, H. Noda, M. Higashida, Y. Okuno, K. Arimoto","doi":"10.1109/ASSCC.2007.4425760","DOIUrl":null,"url":null,"abstract":"This paper describes a real time image processing SoC (MX-SoC) with programmable multi matrix -processor (MX-core) architecture. The MX-SoC has three MX-cores, host-CPU, and I/O peripheral modules. An unit MX-core is a massively parallel (1024) flexible SIMD processor based on the matrix architecture. The MX-SoC, which can perform the image processing of CCD camera, is implemented on 90nm low power CMOS process technology and can operate at 162 MHz under the worst condition. A novel parallel pixel data processing algorithm, and multi task execution suitable for multi MX-core processing can achieve 30 frame/sec image processing. This performance is 30 times faster than general purpose CPU solution. The MX-SoC with multi MX-core architecture can realize the software solution of real time image processing application field.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425760","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper describes a real time image processing SoC (MX-SoC) with programmable multi matrix -processor (MX-core) architecture. The MX-SoC has three MX-cores, host-CPU, and I/O peripheral modules. An unit MX-core is a massively parallel (1024) flexible SIMD processor based on the matrix architecture. The MX-SoC, which can perform the image processing of CCD camera, is implemented on 90nm low power CMOS process technology and can operate at 162 MHz under the worst condition. A novel parallel pixel data processing algorithm, and multi task execution suitable for multi MX-core processing can achieve 30 frame/sec image processing. This performance is 30 times faster than general purpose CPU solution. The MX-SoC with multi MX-core architecture can realize the software solution of real time image processing application field.