T. Yeh, Wei-Yu Wang, Wen-Liang Wang, Yu-Hong Lin, Ying-Lien Cheng, Tsung-Hsin Chou, Jyhfong Lin
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A PCI-express Gen2 transceiver with adaptive 2-Tap DFE for up to 12-meter external cabling
The most updated specification of PCI-Express External Cabling 1.0 only specifies Gen1 (2.5 Gbps) for short-reach usage. This proposed transceiver architecture not only increases the link rate from Genl to Gen2 (5 Gbps), but also extends link range from short-reach to long-reach using a 12-meter 26AWG cable. The S21 of such a cable is -20 dB at 2.5 GHz. The new receiver achieves jitter tolerance at the far-end terminal followed by such a cable is 0.76UI, with a random jitter of 0.31 UI, under the BER of 10-12. This design has been fabricated in TSMC 80 nm CMOS process, with the die area of 0.4 mm2 for each lane.
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