T. Yeh, Wei-Yu Wang, Wen-Liang Wang, Yu-Hong Lin, Ying-Lien Cheng, Tsung-Hsin Chou, Jyhfong Lin
{"title":"A PCI-express Gen2 transceiver with adaptive 2-Tap DFE for up to 12-meter external cabling","authors":"T. Yeh, Wei-Yu Wang, Wen-Liang Wang, Yu-Hong Lin, Ying-Lien Cheng, Tsung-Hsin Chou, Jyhfong Lin","doi":"10.1109/ASSCC.2007.4425788","DOIUrl":null,"url":null,"abstract":"The most updated specification of PCI-Express External Cabling 1.0 only specifies Gen1 (2.5 Gbps) for short-reach usage. This proposed transceiver architecture not only increases the link rate from Genl to Gen2 (5 Gbps), but also extends link range from short-reach to long-reach using a 12-meter 26AWG cable. The S21 of such a cable is -20 dB at 2.5 GHz. The new receiver achieves jitter tolerance at the far-end terminal followed by such a cable is 0.76UI, with a random jitter of 0.31 UI, under the BER of 10-12. This design has been fabricated in TSMC 80 nm CMOS process, with the die area of 0.4 mm2 for each lane.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2007.4425788","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The most updated specification of PCI-Express External Cabling 1.0 only specifies Gen1 (2.5 Gbps) for short-reach usage. This proposed transceiver architecture not only increases the link rate from Genl to Gen2 (5 Gbps), but also extends link range from short-reach to long-reach using a 12-meter 26AWG cable. The S21 of such a cable is -20 dB at 2.5 GHz. The new receiver achieves jitter tolerance at the far-end terminal followed by such a cable is 0.76UI, with a random jitter of 0.31 UI, under the BER of 10-12. This design has been fabricated in TSMC 80 nm CMOS process, with the die area of 0.4 mm2 for each lane.