Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.最新文献_第3页

Formal verification of embedded system designs at multiple levels of abstraction 在多个抽象层次上对嵌入式系统设计进行形式化验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224441

X. Chen, Fang Chen, H. Hsieh, F. Balarin, Yosinori Watanabe

{"title":"Formal verification of embedded system designs at multiple levels of abstraction","authors":"X. Chen, Fang Chen, H. Hsieh, F. Balarin, Yosinori Watanabe","doi":"10.1109/HLDVT.2002.1224441","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224441","url":null,"abstract":"Embedded electronics today are becoming increasingly complex, which makes their design and analysis more and more difficult. An important approach to overcome the increasing complexity is to divide the system design procedure into different but interrelated stages, and represent system designs with description at different levels of abstraction. Design and analysis tools at each stages can then be more effectively applied onto the designs at particular level of abstraction. In this paper, we focus on the formal verification of embedded system designs at multiple levels of abstraction, enabled by the Metropolis design environment. Based on Metropolis framework and the model checker SPIN, a translation mechanism from Metropolis design to Promela description is presented and an automatic translator is developed accordingly. We discuss the challenges and solutions in semantically translating from an object-based system design language to a procedural verification language. To demonstrate the correctness and effectiveness of our approach for formal verification, we verify properties of typical producer-consumer systems.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":" 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133017209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Formal analysis and validation of continuous-time Markov chain based system level power management strategies 基于连续马尔可夫链的系统级电源管理策略的形式化分析与验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224427

G. Norman, D. Parker, M. Kwiatkowska, S. Shukla, Rajesh K. Gupta

{"title":"Formal analysis and validation of continuous-time Markov chain based system level power management strategies","authors":"G. Norman, D. Parker, M. Kwiatkowska, S. Shukla, Rajesh K. Gupta","doi":"10.1109/HLDVT.2002.1224427","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224427","url":null,"abstract":"We have shown in the past that competitive analysis based power management strategies can be automatically analyzed for proving competitive bounds and for validating power management strategies using the SMV model checker. We show that stochastic modelling based strategies for power management can similarly be automated for computing optimal strategies. Further these can be analyzed for finding system parameters for satisfying probabilistic constraints. Effects of any changes in probabilistic assumptions can be easily analyzed without expensive and time consuming simulations. We demonstrate our methodology using the probabilistic model checker PRISM. We model the system using a continuous-time Markov chain, and compute strategies under varying requirements for performance. We also prove probabilistic properties of strategies using PRISM, which gives insight into individual strategies and pragmatics of their implementations. We also show the effects of changing probabilistic assumptions computed by our method and compare the results with other stochastic analysis based methods, and show that we obtain similar results in a uniform framework of probabilistic model checking.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122451802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

High level validation of next-generation microprocessors 下一代微处理器的高级验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224424

B. Bentley

引用次数: 37

Checking temporal properties in SystemC specifications 检查SystemC规范中的时间属性

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224423

A. Braun, J. Gerlach, W. Rosenstiel

{"title":"Checking temporal properties in SystemC specifications","authors":"A. Braun, J. Gerlach, W. Rosenstiel","doi":"10.1109/HLDVT.2002.1224423","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224423","url":null,"abstract":"Today's system designs consist of multiple architectural components, software as well as hardware. The ability to specify and verify these systems at a high level of abstraction is a key competence to cope with the increasing design complexity. C/C++ based approaches on system specification and design are becoming more and more important. They provide a common platform for system designers, hardware and software engineers, and allow a high-performant simulation of system's behavior during the whole design process. The leading approach for C++ based system specification is SystemC which is on the step of becoming a de facto standard in industrial system-level design. Generally, within SystemC the testbench of a design will also be specified in SystemC, which results in a tight coupling of the design and the corresponding test environment. On the other hand, only rudimentary testbench support is given in SystemC and sophisticated features of today's testbench environments are missing. The checking of temporal properties is one of the core requirements in the area of functional verification and is not supported by the standard SystemC language. This paper addresses that important problem. It shows strategies for checking temporal properties in a SystemC design in terms of an easy-to-understand application, a traffic light controller.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"359 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122852000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

VHDL-based simulation environment for Proteo NoC 基于vhdl的Proteo NoC仿真环境

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224419

David A. Sigüenza-Tortosa, J. Nurmi

引用次数: 48

An equivalence checking methodology for hardware oriented C-based specifications 面向硬件的基于c语言规范的等价性检查方法

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224443

H. Saito, Takaya Ogawa, T. Sakunkonchak, M. Fujita, T. Nanya

引用次数: 19

X-Gen: a random test-case generator for systems and SoCs X-Gen:系统和soc的随机测试用例生成器

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224444

Roy Emek, Itai Jaeger, Y. Naveh, Gadi Bergman, Guy Aloni, Yoav Katz, Monica Farkash, Igor Dozoretz, Alex Goldin

引用次数: 63

TRANS: efficient sequential verification of loop-free circuits TRANS:无环路电路的有效顺序验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224439

Z. Khasidashvili, J. Moondanos, Z. Hanna

引用次数: 7

Using Aspect-GAMMA in the design of embedded systems 在嵌入式系统设计中使用Aspect-GAMMA

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224431

M. Mousavi, G. Russello, M. Chaudron, M. Reniers, T. Basten, A. Corsaro, S. Shukla, Rajesh K. Gupta, D. Schmidt

引用次数: 20

Verification of a DSP IP cores by model checking DSP IP核的模型验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224440

H. Nguyen, P. Koumou, B. Candaele, Michel Sarlotte, C. Antoine, S. Emeriau

引用次数: 0