An equivalence checking methodology for hardware oriented C-based specifications

Abstract

Verification to validate designs is one of the important tasks in VLSI design flow. Due to the great advances in integration, verification for whole designs is getting more and more difficult. To solve this problem in early stages of design flows, we suggest a formal equivalence checking method for given two C-based hardware oriented specifications (C descriptions). To verify large C descriptions efficiently, we use textual differences in the two C descriptions and verify them in terms, of symbolic simulation. We believe that our approach will be useful where two specifications to be verified are very close, which is a very common situation in practical designs.