Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.最新文献

Slightly-off-specification failures in the time-triggered architecture 在时间触发的体系结构中出现轻微的不规范故障

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224420

A. Ademaj

引用次数: 30

An effective and flexible approach to functional verification of processor families 一种有效而灵活的处理器系列功能验证方法

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224435

David Malandain, Pim Palmen, M.B. Taylor, M. Aharoni, Yaron Arbetman

引用次数: 10

Experimental validation of fault detection and fault tolerance mechanisms 故障检测与容错机制的实验验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224450

P. Gawkowski, J. Sosnowski

引用次数: 7

A 1000X speed up for properties completeness evaluation 属性完整性评估的速度提高了1000倍

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224422

A. Castelnuovo, A. Fedeli, A. Fin, F. Fummi, G. Pravadelli, U. Rossi, F. Sforza, F. Toto

引用次数: 6

Generating concurrent test-programs with collisions for multi-processor verification 为多处理器验证生成带有冲突的并发测试程序

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224432

Allon Adir, G. Shurek

引用次数: 26

Adaptive test program generation: planning for the unplanned 自适应测试程序生成:为计划外的项目做计划

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224433

Allon Adir, Roy Emek, E. Marcus

引用次数: 6

A simple and effective compression scheme for test pins reduction 一个简单有效的压缩方案，测试销减少

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224447

M. Flottes, Regis Poirier, B. Rouzeyre

引用次数: 1

A hierarchical approach for designing dependable systems 设计可靠系统的分层方法

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224430

M. Reorda, M. Violante, N. Mazzocca, S. Venticinque, A. Bobbio, G. Franceschinis

引用次数: 1

Setting break-points in distributed time-triggered architecture 在分布式时间触发架构中设置断点

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224429

Idriz Smaili, A. Ademaj

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引用次数: 1

Automatic functional test program generation for pipelined processors using model checking 使用模型检查的流水线处理器自动功能测试程序生成

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224436

P. Mishra, N. Dutt

引用次数: 32