Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.最新文献_第2页

Timed HW-SW cosimulation using native execution of OS and application SW 使用操作系统和应用软件的本机执行定时HW-SW协同仿真

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224428

Iuliana Bacivarov, S. Yoo, A. Jerraya

引用次数: 28

Prototyping of embedded digital systems from SDL language: a case study 基于SDL语言的嵌入式数字系统原型设计:一个案例研究

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224442

C. Marcon, Fabiano Hessel, Alexandre M. Amory, Luis H. L. Ries, F. Moraes, Ney Laert Vilar Calazans

引用次数: 6

Test generation for hardware-software covalidation using non-linear programming 使用非线性编程的硬件软件共验证测试生成

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224449

Fei Xin, I. Harris

引用次数: 6

Breaking an application specific instruction-set processor: the first step towards embedded software testing 打破应用程序特定指令集处理器:迈向嵌入式软件测试的第一步

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224434

J. Dielissen, B. O. Mathijssen, J. Huisken

引用次数: 0

Taking the best out of two worlds: prototyping and hardware emulation 充分利用两个世界:原型设计和硬件仿真

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224446

M. Wannemacher, M. Munteanu, S. Perret, R. Singer

引用次数: 2

Constructing reusable testbenches 构建可重用的测试平台

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224445

A. Wakefield, B. Mohd

引用次数: 2

Practical experiences in functional simulation. An integrated method from unit to co-simulation 具有功能仿真方面的实践经验。从单元到联合仿真的集成方法

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224426

Klaus-Dieter Schubert

{"title":"Practical experiences in functional simulation. An integrated method from unit to co-simulation","authors":"Klaus-Dieter Schubert","doi":"10.1109/HLDVT.2002.1224426","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224426","url":null,"abstract":"IBM, like other major companies, is developing large compute servers. These servers run typically various applications supported on a variety of different operating systems. To support all the user scenarios the systems consist of a hardware layer and a system software layer, that is hidden from the application or operating system. The hardware consists of a set of chips where some are unique for a given series of compute server. The system software, also called firmware, can be viewed as an extension of the hardware, to enable additional features and to manage those complex systems. From a verification point of view the task is to make sure that first of all the hardware chips are working according to the specification, that all these chips are also working together and nevertheless the firmware code is working seamlessly with the hardware. To complicate the task, the chip designs are following not always the same methodology, driven by the fact that we have a mix of custom designed VLSI chips, standard ASIC designs and some SoC type chips. With teams distributed globally the verification challenge is to integrate and coordinate all efforts to finally ensure that the overall system is working. The presentation will describe the problems and possible solutions, touching topics like standardization of interfaces, designs and languages, reusability of specifications, documentation and software, project managing aspects and their implications on the process.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120945129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-level and hierarchical test sequence generation 高级和分层的测试序列生成

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224448

G. Jervan, Zebo Peng, O. Goloubeva, M. Reorda, M. Violante

引用次数: 41

High-level design verification using Taylor Expansion Diagrams: first results 使用泰勒展开图的高级设计验证:第一个结果

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224421

P. Kalla, M. Ciesielski, E. Boutillon, E. Martin

引用次数: 13

Alignability equivalence of synchronous sequential circuits 同步顺序电路的可对准性等效

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224438

A. Rosenmann, Z. Hanna

{"title":"Alignability equivalence of synchronous sequential circuits","authors":"A. Rosenmann, Z. Hanna","doi":"10.1109/HLDVT.2002.1224438","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224438","url":null,"abstract":"Sequential verification is a well known research framework that has attracted many researchers in the aca demic and industrial worlds during the last few decades. In this framework, initialization of synchronous models is one of the fundamental and challenging research topics that is difficult to solve, especially when talking about large industrial strengths hardware models. Many researchers in this domain such as Pomeranz and Reddy (1994), Pixley and Beihl (1991), and Pixley, Jeong and Hachtel (1994), and others tried to analyze and propose solutions to this problem, however the majority of the approaches used were based on BDDs and classical reachability analysis methods, which by nature suffer from capacity and complexity limits. When talking about hardware formal equivalence verification, the Initialization issue becomes even more complex especially when trying to verify the logic equivalence of two large industrial circuits. In this note we propose a new adaptive and iterative approach that combines various symbolic simulation techniques and bounded model checking algorithms to initialize sequential circuits for the alignability equivalence verification. The novelty of our method has been employed on complex real life sequential models from Intel lead Pentium processor designs. These methods are already implemented in Intel's sequential verification engine, Insight.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132734774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11