Ranan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdelillah Mokkedem
{"title":"Accelerated verification of RTL assertions based on satisfiability solvers","authors":"Ranan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdelillah Mokkedem","doi":"10.1109/HLDVT.2002.1224437","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224437","url":null,"abstract":"RTL assertions play an increasing role in the validation process. The high capacity and usability of Bounded Model Checking (BMC) make it especially attractive for the verification of such assertions. However, BMC is usually used to check a single property for a given bound, while here we are dealing with hundreds of properties each one requiring a different bound. We propose in this paper a new BMC algorithm that checks multiple properties simultaneously, and yet it is able to detect which properties failed or passed on an individual basis., Moreover, we show that our verification checks are stronger, as they can succeed in proving more properties than the classic algorithm.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129249731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Top-level validation of system-on-chip in Esterel Studio","authors":"G. Berry, Lionel Blanc, A. Bouali, Jerome Dormoy","doi":"10.1109/HLDVT.2002.1224425","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224425","url":null,"abstract":"We present a new tool-supported methodology for system on chip top-level validation (TLV). The addressed problem is the systematic validation of IP interaction to ensure correct global functional behavior of a SoC design, assuming that each IP has been individually validated. The goal is to generate functional tests for the final design that cover the interaction behavior in a systematic, well-defined, and complete way. The typical problem to be found is incorrect inter-IP data flow due to misconfiguration or missynchronization of IPs. The tool is Esterel Studio, a design and verification environment based on the SyncCharts hierarchical concurrent finite state machine (HFSM) formalism. SynchCharts are a graphical variant of the Esterel high-level synchronous programming language, which is used to specify and synthesize circuits and embedded software.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127172555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}