Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.最新文献

筛选
英文 中文
Accelerated verification of RTL assertions based on satisfiability solvers 基于可满足性求解器的RTL断言的加速验证
Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224437
Ranan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdelillah Mokkedem
{"title":"Accelerated verification of RTL assertions based on satisfiability solvers","authors":"Ranan Fraer, Shahid Ikram, Gila Kamhi, Tim Leonard, Abdelillah Mokkedem","doi":"10.1109/HLDVT.2002.1224437","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224437","url":null,"abstract":"RTL assertions play an increasing role in the validation process. The high capacity and usability of Bounded Model Checking (BMC) make it especially attractive for the verification of such assertions. However, BMC is usually used to check a single property for a given bound, while here we are dealing with hundreds of properties each one requiring a different bound. We propose in this paper a new BMC algorithm that checks multiple properties simultaneously, and yet it is able to detect which properties failed or passed on an individual basis., Moreover, we show that our verification checks are stronger, as they can succeed in proving more properties than the classic algorithm.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129249731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Top-level validation of system-on-chip in Esterel Studio 在Esterel Studio中对片上系统进行顶层验证
Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI: 10.1109/HLDVT.2002.1224425
G. Berry, Lionel Blanc, A. Bouali, Jerome Dormoy
{"title":"Top-level validation of system-on-chip in Esterel Studio","authors":"G. Berry, Lionel Blanc, A. Bouali, Jerome Dormoy","doi":"10.1109/HLDVT.2002.1224425","DOIUrl":"https://doi.org/10.1109/HLDVT.2002.1224425","url":null,"abstract":"We present a new tool-supported methodology for system on chip top-level validation (TLV). The addressed problem is the systematic validation of IP interaction to ensure correct global functional behavior of a SoC design, assuming that each IP has been individually validated. The goal is to generate functional tests for the final design that cover the interaction behavior in a systematic, well-defined, and complete way. The typical problem to be found is incorrect inter-IP data flow due to misconfiguration or missynchronization of IPs. The tool is Esterel Studio, a design and verification environment based on the SyncCharts hierarchical concurrent finite state machine (HFSM) formalism. SynchCharts are a graphical variant of the Esterel high-level synchronous programming language, which is used to specify and synthesize circuits and embedded software.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127172555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信