在Esterel Studio中对片上系统进行顶层验证

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI:10.1109/HLDVT.2002.1224425

G. Berry, Lionel Blanc, A. Bouali, Jerome Dormoy

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引用次数: 8

摘要

我们提出了一种新的工具支持的片上系统顶层验证(TLV)方法。解决的问题是IP交互的系统验证，以确保SoC设计的正确全局功能行为，假设每个IP都已单独验证。目标是为最终设计生成功能测试，以系统的、良好定义的和完整的方式覆盖交互行为。典型的问题是由于ip配置错误或ip不同步导致的ip间数据流错误。该工具是Esterel Studio，一个基于SyncCharts分层并发有限状态机(HFSM)形式的设计和验证环境。SynchCharts是Esterel高级同步编程语言的图形化变体，用于指定和合成电路和嵌入式软件。

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Top-level validation of system-on-chip in Esterel Studio

We present a new tool-supported methodology for system on chip top-level validation (TLV). The addressed problem is the systematic validation of IP interaction to ensure correct global functional behavior of a SoC design, assuming that each IP has been individually validated. The goal is to generate functional tests for the final design that cover the interaction behavior in a systematic, well-defined, and complete way. The typical problem to be found is incorrect inter-IP data flow due to misconfiguration or missynchronization of IPs. The tool is Esterel Studio, a design and verification environment based on the SyncCharts hierarchical concurrent finite state machine (HFSM) formalism. SynchCharts are a graphical variant of the Esterel high-level synchronous programming language, which is used to specify and synthesize circuits and embedded software.

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Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.

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