Top-level validation of system-on-chip in Esterel Studio

Abstract

We present a new tool-supported methodology for system on chip top-level validation (TLV). The addressed problem is the systematic validation of IP interaction to ensure correct global functional behavior of a SoC design, assuming that each IP has been individually validated. The goal is to generate functional tests for the final design that cover the interaction behavior in a systematic, well-defined, and complete way. The typical problem to be found is incorrect inter-IP data flow due to misconfiguration or missynchronization of IPs. The tool is Esterel Studio, a design and verification environment based on the SyncCharts hierarchical concurrent finite state machine (HFSM) formalism. SynchCharts are a graphical variant of the Esterel high-level synchronous programming language, which is used to specify and synthesize circuits and embedded software.