A simple and effective compression scheme for test pins reduction

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI:10.1109/HLDVT.2002.1224447

M. Flottes, Regis Poirier, B. Rouzeyre

引用次数: 1

Abstract

We present a simple and effective method for test pin reduction. It must be noticed first that this method is particularly well adapted to the test of SoC since it only deals with test data and does not require any knowledge of the embedded cores. Secondly, it does not induce any delay penalty neither in the circuit itself nor during decompression.

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一个简单有效的压缩方案，测试销减少

提出了一种简单有效的减小测试引脚的方法。首先必须注意的是，这种方法特别适合SoC的测试，因为它只处理测试数据，不需要任何嵌入式内核的知识。其次，无论是在电路本身还是在解压缩过程中，它都不会引起任何延迟惩罚。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.

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