{"title":"故障检测与容错机制的实验验证","authors":"P. Gawkowski, J. Sosnowski","doi":"10.1109/HLDVT.2002.1224450","DOIUrl":null,"url":null,"abstract":"The paper deals with the problem of validating the effectiveness of hardware and software mechanisms decreasing system susceptibility to hardware faults. The validation process is based on the use of software implemented fault injector (FITS). The performed analysis concentrates on tuning the profile of faults and experiment set-ups. The presented simulation results are explained in context of the considered applications.","PeriodicalId":179418,"journal":{"name":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Experimental validation of fault detection and fault tolerance mechanisms\",\"authors\":\"P. Gawkowski, J. Sosnowski\",\"doi\":\"10.1109/HLDVT.2002.1224450\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper deals with the problem of validating the effectiveness of hardware and software mechanisms decreasing system susceptibility to hardware faults. The validation process is based on the use of software implemented fault injector (FITS). The performed analysis concentrates on tuning the profile of faults and experiment set-ups. The presented simulation results are explained in context of the considered applications.\",\"PeriodicalId\":179418,\"journal\":{\"name\":\"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-10-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HLDVT.2002.1224450\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HLDVT.2002.1224450","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Experimental validation of fault detection and fault tolerance mechanisms
The paper deals with the problem of validating the effectiveness of hardware and software mechanisms decreasing system susceptibility to hardware faults. The validation process is based on the use of software implemented fault injector (FITS). The performed analysis concentrates on tuning the profile of faults and experiment set-ups. The presented simulation results are explained in context of the considered applications.