Formal verification of embedded system designs at multiple levels of abstraction

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002. Pub Date : 2002-10-27 DOI:10.1109/HLDVT.2002.1224441

X. Chen, Fang Chen, H. Hsieh, F. Balarin, Yosinori Watanabe

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引用次数: 15

Abstract

Embedded electronics today are becoming increasingly complex, which makes their design and analysis more and more difficult. An important approach to overcome the increasing complexity is to divide the system design procedure into different but interrelated stages, and represent system designs with description at different levels of abstraction. Design and analysis tools at each stages can then be more effectively applied onto the designs at particular level of abstraction. In this paper, we focus on the formal verification of embedded system designs at multiple levels of abstraction, enabled by the Metropolis design environment. Based on Metropolis framework and the model checker SPIN, a translation mechanism from Metropolis design to Promela description is presented and an automatic translator is developed accordingly. We discuss the challenges and solutions in semantically translating from an object-based system design language to a procedural verification language. To demonstrate the correctness and effectiveness of our approach for formal verification, we verify properties of typical producer-consumer systems.

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在多个抽象层次上对嵌入式系统设计进行形式化验证

当今的嵌入式电子产品越来越复杂，这使得其设计和分析变得越来越困难。将系统设计过程划分为不同但又相互关联的阶段，并用不同抽象层次的描述来表示系统设计，是克服系统设计复杂性的重要方法。然后，每个阶段的设计和分析工具可以更有效地应用于特定抽象级别的设计。在本文中，我们着重于在多个抽象层次上对嵌入式系统设计的形式化验证，这些设计是由Metropolis设计环境实现的。基于Metropolis框架和模型检查器SPIN，提出了从Metropolis设计到Promela描述的翻译机制，并据此开发了自动翻译器。我们讨论了从基于对象的系统设计语言到过程验证语言的语义转换所面临的挑战和解决方案。为了证明我们的形式化验证方法的正确性和有效性，我们验证了典型的生产者-消费者系统的属性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.

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