High level validation of next-generation microprocessors

Abstract

Moore's Law continues to drive an inexorable increase in the number of transistors that can be integrated onto a single die. Computer architects continue to find ways to use all of these transistors to design ever more complex microprocessors. At the same time, competitive pressures are dictating shorter design cycles and faster time to market, while design team size has reached (and perhaps exceeded) the limit beyond which further growth is impracticable. This paper outlines some of the approaches being considered to address the challenge of validating Intel's next-generation IA32 microarchitecture. Building on the lessons learned from validating the Pentium/spl reg/ 4 processor, it addresses the role of a higher-level abstraction (above the current RTL model) and a broader application of formal verification techniques to the validation problem.