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Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing最新文献

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A tribute to graphics DRAMs 向图形dram致敬
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782693
B. Prince
{"title":"A tribute to graphics DRAMs","authors":"B. Prince","doi":"10.1109/MTDT.1999.782693","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782693","url":null,"abstract":"High speed graphics subsystems used some of the earliest application specific DRAMs. Knowledge gained from working with these specialized parts has provided a background for many of the innovations seen today in high speed DRAMs, fast core DRAMs, and high bandwidth embedded DRAMs. Years before synchronous DRAMs become common, clocked DRAM field memories for television frame buffers were in production. The later Video DRAMs were precursors for EDO page mode, dual bank architecture, synchronous operation, and high bandwidth through use of a wide internal bus. Implementations for graphics subsystems today continue to spearhead the emerging area of embedded DRAMs and parallel processing.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116862983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power SRAM circuit design 低功耗SRAM电路设计
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782692
M. Margala
{"title":"Low-power SRAM circuit design","authors":"M. Margala","doi":"10.1109/MTDT.1999.782692","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782692","url":null,"abstract":"This paper presents an extensive summary of the latest developments in low-power circuit techniques and methods for Static Random Access Memories. The key techniques in power reduction in both active and standby modes are: capacitance reduction by using divided word-line structure or single-bitline cross-point cell activation, pulse operation by using ATD generator and reduced signal swings on high-capacitance predecode lines, write bus lines and datalines, AC current reduction by using multistage decoding, operating voltage reduction coupled with low-power sensing by using charge-transfer amplification, step-down boosted word-line scheme or full current-mode read/write operation and leakage current suppression by using dual-Vt, Auto-Backgate-Controlled multiple-Vt, or dynamic leakage cut-off techniques.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122061067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
The potential of carbon-based memory systems 碳基存储系统的潜力
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782691
Mark Brehob, R. Enbody
{"title":"The potential of carbon-based memory systems","authors":"Mark Brehob, R. Enbody","doi":"10.1109/MTDT.1999.782691","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782691","url":null,"abstract":"It seems likely that density concerns will force the DRAM community to consider using radically different schemes for the implementation of memory devices. We propose using nano-scale carbon structures as the basis for a memory device. A single-wall carbon nanotube would contain a charged buckyball. That buckyball will stick tightly to one end of the tube or the other. We assign the bit value of the device depending on which side of the tube the ball is. The result is a high-speed, non-volatile bit of memory. We propose a number of schemes for the interconnection of these devices and examine some of the known electrical issues.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128045606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Built in self test for ring addressed FIFOs with transparent latches 内置自检环寻址fifo与透明锁存器
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782686
L. Fenstermaker, Ilyoung Kim, J. Lewandowski, J. J. Nagy
{"title":"Built in self test for ring addressed FIFOs with transparent latches","authors":"L. Fenstermaker, Ilyoung Kim, J. Lewandowski, J. J. Nagy","doi":"10.1109/MTDT.1999.782686","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782686","url":null,"abstract":"The use of special purpose complex embedded memories is becoming increasingly common. Their complex functionality, large sizes, decreasing feature sizes, and limited controllability/observability combine to make testing ever more difficult. In this paper, we describe a built in self test (BIST) method for testing ring addressed first in first out memories (FIFOs) that use transparent input latches for applications that require high data rates. The method used is compared to previous results for ring addressed FIFOs with edge triggered input latches. Several different special test modes are used to provide both more efficient and more complete BIST.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133290235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Computing in memory architectures for digital image processing 用于数字图像处理的存储器结构计算
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782678
L. Roth, L. D. Coraor, D. Landis, P. T. Hulina, S. Deno
{"title":"Computing in memory architectures for digital image processing","authors":"L. Roth, L. D. Coraor, D. Landis, P. T. Hulina, S. Deno","doi":"10.1109/MTDT.1999.782678","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782678","url":null,"abstract":"Continuing improvements in semiconductor fabrication density are enabling new classes of system-on-a-chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these new architectures can be custom tailored to the demands of real-time digital image processing. This paper evaluates several candidate designs, using the criteria of image processing performance, flexibility, manufacturability, and fabrication cost.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117279500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Modeling and testing transistor faults in content-addressable memories 内容可寻址存储器中晶体管故障的建模和测试
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782688
P. R. Sidorowicz
{"title":"Modeling and testing transistor faults in content-addressable memories","authors":"P. R. Sidorowicz","doi":"10.1109/MTDT.1999.782688","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782688","url":null,"abstract":"A behavioral analysis of transistor faults and cell-stuck-at faults in a n-word by l-bit static CMOS CAM array is presented. First, a CAM cell is analyzed at the transistor-network, event-sequence and finite-state machine level. Then, a transistor stuck-(on/open) and cell-stuck-at fault model for a CAM is defined. We show that two out of eighteen possible CAM cell's transistor faults cannot be tested reliably by functional tests; however among faults that are testable, are all those which comprise data-retention faults. We also show that a test, originally designed to detect input stuck-at faults, also detects all reliably testable transistor faults and all cell-stuck-at faults in the model.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"401 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124271468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A fast test to generate flash memory threshold voltage distribution map 快速测试生成闪存阈值电压分布图
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782687
Raju Khubchandani
{"title":"A fast test to generate flash memory threshold voltage distribution map","authors":"Raju Khubchandani","doi":"10.1109/MTDT.1999.782687","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782687","url":null,"abstract":"This paper describes a method to determine threshold voltage (V/sub th/) distribution as a multi-colored bitmap of the die. That is, a visual indication of relative threshold voltages on different areas of the die is provided. The spatial distribution of threshold voltage is felt to be more informative than conventional techniques which provide results as a bell-curve Gauss distribution plot of threshold voltage versus number of cells. The time required for test execution (including data gathering) is considerably less than the time taken by conventional methods.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129136555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Determining redundancy requirements for memory arrays with critical area analysis 通过关键区域分析确定存储器阵列的冗余要求
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782683
J. Segal, S. Bakarian, J. E. Colburn, Madan Kumar, Chang Hong, A. Shubat
{"title":"Determining redundancy requirements for memory arrays with critical area analysis","authors":"J. Segal, S. Bakarian, J. E. Colburn, Madan Kumar, Chang Hong, A. Shubat","doi":"10.1109/MTDT.1999.782683","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782683","url":null,"abstract":"Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124395055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Tutorial: characterizing SDRAMs 教程:表征dram
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782685
J. Voilrath
{"title":"Tutorial: characterizing SDRAMs","authors":"J. Voilrath","doi":"10.1109/MTDT.1999.782685","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782685","url":null,"abstract":"This paper presents characterization methods for an SDRAM in a manufacturing environment. Contact tests, dc tests, basic functional tests, signal margin tests and retention characterization are shown. Measurement of the cell signal is used as an example for pico probing. Special test modes for SDRAMs which can be used to aid characterization and failure analysis (FA) are discussed.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"61 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120843694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval 动态关联存取存储器芯片及其在SIMD处理和全文数据库检索中的应用
Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI: 10.1109/MTDT.1999.782680
G. Lipovski, Clement T. Yu
{"title":"The dynamic associative access memory chip and its application to SIMD processing and full-text database retrieval","authors":"G. Lipovski, Clement T. Yu","doi":"10.1109/MTDT.1999.782680","DOIUrl":"https://doi.org/10.1109/MTDT.1999.782680","url":null,"abstract":"Dynamic Associative Access Memory (DAAM) chips are processor-in-memory chips wherein a large number of small processing elements are put in a DRAM's sense amps. Thousands of these chips will be mounted on \"memory boards\" in \"TONY\" full-text database servers. This paper shows that multibank memory eliminates DRAM latency, and a one-bit ALU that can be made into an associative processor, with the addition of one gate. This paper shows how this unconventional technology offers nearly three orders of magnitude better cost performance than a Pentium microprocessor, nearly 1,000 MIPs per dollar of chip cost for the DAAM compared to about 1 MIPs per dollar of chip cost for the Pentium. This paper shows that a TONY server system using this chip will handle over a million on-line users, more than two orders of magnitude more cost-effective than the best current database machines, and a TONY server stores a page of text for approximately five cents (the cost of duplicating the printed page).","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131091515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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