通过关键区域分析确定存储器阵列的冗余要求

Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing Pub Date : 1999-08-09 DOI:10.1109/MTDT.1999.782683

J. Segal, S. Bakarian, J. E. Colburn, Madan Kumar, Chang Hong, A. Shubat

{"title":"通过关键区域分析确定存储器阵列的冗余要求","authors":"J. Segal, S. Bakarian, J. E. Colburn, Madan Kumar, Chang Hong, A. Shubat","doi":"10.1109/MTDT.1999.782683","DOIUrl":null,"url":null,"abstract":"Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations.","PeriodicalId":166999,"journal":{"name":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Determining redundancy requirements for memory arrays with critical area analysis\",\"authors\":\"J. Segal, S. Bakarian, J. E. Colburn, Madan Kumar, Chang Hong, A. Shubat\",\"doi\":\"10.1109/MTDT.1999.782683\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations.\",\"PeriodicalId\":166999,\"journal\":{\"name\":\"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.1999.782683\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.1999.782683","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 20

摘要

利用内联缺陷数据、单元布局的关键区域分析以及将关键区域与电气故障关联的基于规则的算法，我们可以确定任何存储电路的最佳冗余配置。该技术预测了一系列冗余配置的产量，并根据产量和模具尺寸的考虑，找到任何存储器设计的最佳冗余行和列数。

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Determining redundancy requirements for memory arrays with critical area analysis

Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations.

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Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing

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