Yusuke Osawa, D. Hirabayashi, Naohiro Harigai, Haruo Kobayashi, K. Niitsu, O. Kobayashi
{"title":"Phase noise measurement techniques using delta-sigma TDC","authors":"Yusuke Osawa, D. Hirabayashi, Naohiro Harigai, Haruo Kobayashi, K. Niitsu, O. Kobayashi","doi":"10.1109/IMS3TW.2014.6997392","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997392","url":null,"abstract":"This paper describes two techniques for measuring phase noise of a clock using a delta-sigma time-to-digital converter (TDC). One technique uses a reference signal (which has only very small phase noise), and the other does not use a reference signal. Both proposed techniques can be implemented with relatively simple circuitry, due to the following: (i) The clock under test (CUT) is a repetitive signal. (ii) The time resolution with CUT and a reference clock can be increased by using longer measurement time with the delta-sigma TDC. (iii) The phase noise power spectrum can be calculated from the delta-sigma TDC output data using FFT. Costly high-performance spectrum analyzers which average several-time phase measurement results over a long measurement time (about 10s order), are not needed for phase noise measurement with the proposed technique. The other technique, which differs in that it uses a self-referenced clock rather than a reference signal, has potential wide applications.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117346395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ATPG for mixed-signal circuits using commercial digital tools","authors":"C. Wegener","doi":"10.1109/IMS3TW.2014.6997394","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997394","url":null,"abstract":"For digital circuits, Automatic Test Pattern Generation (ATPG) is a commercially solved problem. For circuits which contain analog components, intensive research and some commercial approaches are available.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126777679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Chang, J. Patel, Haleh Shahbazbegian, B. Kaminska
{"title":"An electro-chemical test and optimization system for impressed current cathodic corrosion protection","authors":"A. Chang, J. Patel, Haleh Shahbazbegian, B. Kaminska","doi":"10.1109/IMS3TW.2014.6997399","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997399","url":null,"abstract":"A simple electro-chemical test and an optimization system for impressed current cathodic protection (ICCP) for the A36 hot-rolled steel bar is presented in this article. A simple two-electrode based test system using an electro-chemical cell to test the corrosion rate of the target metal is proposed. The Tafel plot to determine the corrosion rate of the target metal is prepared using our simple test system and the corrosion current (icorr) is extrapolated from the Tafel plot. A novel technique by impressing the corrosion current to protect the target metal using ICCP is implemented and tested. The proposed protection system further simplifies the corrosion protection system compared to the current methods. To determine effectiveness of the proposed protection system, weight loss of a freely corroding target metal and a protected sample of the target metal are compared. For 0.6 M NaCl solution as a test environment, both the metal samples are tested for two weeks. The protected metal sample is protected using our novel closed-loop protection system using 2.4 - 4.25 mW power with protection feedback every 24 hours. The weight reduction of the freely corroding metal sample is 0.017533 weight percentage per day and for the protected metal sample is 0.003357 weight percentage per day. Hence, the weight lost of the freely corroded metal is 5.22 times faster than the protected metal sample.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131290123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Dieng, F. Azais, M. Comte, S. Bernard, V. Kerzérho, M. Renovell, T. Kervaon, P. Pugliesi-Conti
{"title":"Study of adaptive tuning strategies for Near Field Communication (NFC) transmitter module","authors":"M. Dieng, F. Azais, M. Comte, S. Bernard, V. Kerzérho, M. Renovell, T. Kervaon, P. Pugliesi-Conti","doi":"10.1109/IMS3TW.2014.6997401","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997401","url":null,"abstract":"In this paper, adaptive tuning strategies for Near Field Communication (NFC) transmitter module are investigated. The objective is to perform auto-adjustment of the matching network associated with the transmitter antenna in order to compensate the influence of the receiver antenna. Two different strategies are studied, aiming at maintaining a constant emitted magnetic field or a constant current consumption.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115358504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Antonio Jose Salazar Escobar, J. Machado da Silva, M. Correia
{"title":"An I2C based mixed-signal test and measurement infrastructure","authors":"Antonio Jose Salazar Escobar, J. Machado da Silva, M. Correia","doi":"10.1109/IMS3TW.2014.6997396","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997396","url":null,"abstract":"The framework being proposed addresses the test and measurement of circuits and systems populated with varying types of sensors and functional blocks, among which one can find embedded test instruments. Its conceptual functionality is based on four types of operations: setup, capture, process, and scan (SCPS), and aims to provide a unifying methodology for managing and synchronizing test operations and instruments. The generalized physical structure and examples of operating commands are described. An application illustrates its use in a particular case.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130522592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Athanasios Dimakos, H. Stratigopoulos, A. Siligaris, S. Mir, E. de Foucauld
{"title":"Non-intrusive built-in test for 65nm RF LNA","authors":"Athanasios Dimakos, H. Stratigopoulos, A. Siligaris, S. Mir, E. de Foucauld","doi":"10.1109/IMS3TW.2014.6997397","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997397","url":null,"abstract":"In this paper, we discuss the use of non-intrusive sensors to enable a built-in test for a 65nm RF LNA. The non-intrusive sensors consist of single layout components copied from the topology of the LNA and dummy analog stages formed by identical components used in the topology of the LNA. The sensors are placed in close physical proximity to the LNA such that the sensor measurements track the performances of the LNA by virtue of die-to-die and correlated within-die process variations. In this way, the alternate test paradigm is used to infer the performances from the sensor measurements. Although the correlation between sensor measurements and performances is negatively affected by the uncorrelated within-die variations, we show that the correlation still holds strong even for the advanced 65nm technology node where this type of variations is more pronounced. In addition, we show that instead of using dummy area-hungry inductors to monitor inductance variability, we can obtain the same level of correlation by monitoring instead the sheet resistances of the metal lines that form the coil of the inductors.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125214555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. L. da Silva, E. Camargo, Douglas Foster, Sandro T. Coelho, A. G. de Oliveira, A. Olmos, M. Lubaszewski
{"title":"Low cost test architecture for mixed-signal integrated circuits","authors":"J. L. da Silva, E. Camargo, Douglas Foster, Sandro T. Coelho, A. G. de Oliveira, A. Olmos, M. Lubaszewski","doi":"10.1109/IMS3TW.2014.6997389","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997389","url":null,"abstract":"Mixed-signal integrated circuit testability is a complex problem because test circuitry must satisfy conflicting constraints, such as low area and power meanwhile achieving reduced test time. This paper presents a complete solution that enhances the state of the art towards testability of mixed-signal circuits, based on a 3-pin interface. This solution encompasses an efficient low cost test architecture that enables structural and functional tests of mixed-signal circuits. Experimental results demonstrate the proposed architecture flexibility applied to applications with diverse test requirements.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134561770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Suvadeep Banerjee, D. Banerjee, A. Banerjee, Kyungmin Lee, A. Chatterjee
{"title":"Low cost implicit built-in self-test of passive RFID Tags","authors":"Suvadeep Banerjee, D. Banerjee, A. Banerjee, Kyungmin Lee, A. Chatterjee","doi":"10.1109/IMS3TW.2014.6997390","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997390","url":null,"abstract":"Testing of RFID Tags is complicated by the fact that the RFID chips must be tested both before and after antenna attach. The test procedure prior to chip attach must ensure, to the maximum extent possible, that any defects in the chip that can cause failure after antenna attach are detected with very high failure coverage. The test procedure after antenna attach must ensure that no failures are injected into the system during the antenna attach procedure itself. In both cases, the metric of performance that the RFID system is assessed against, is the maximum distance between the tag reader and the RFID tag at which reliable communication is established between the two. Since RFID tags are extremely low cost, BIST techniques for both test procedures are developed for inductively coupled RFID tags (ISM Band of 13.56 MHz) that are ultra low cost and require minimal hardware overhead (to justify cost considerations). It is shown that high manufacturing failure coverage is achieved with very low BIST overhead.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"543 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116227204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault mitigation strategies for Single Event Transients on SAR converters","authors":"A. J. C. Lanot, T. Balen","doi":"10.1109/IMS3TW.2014.6997395","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997395","url":null,"abstract":"In this work, we analyze the resilience of SAR converters based on charge redistribution against Single Event Transients. These effects may be mitigated using well-known Fault Tolerance techniques. However, each strategy has its advantages and disadvantages, which may affect the area, power consumption, as well as the linearity of the circuit. This paper shows possible alternatives for the best trade-off approach on the design of such converters. Investigations were conducted by means of an extensive fault injection campaign in an 8-bit architecture modeled in SPICE, considering a 130nm predictive technology model.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"367 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134517417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takeshi Chujo, D. Hirabayashi, Congbing Li, Yutaro Kobayashi, Junshan Wang, Haruo Kobayashi, Kentaroh Katoh, Sato Koshi
{"title":"Experimental verification of timing measurement circuit with self-calibration","authors":"Takeshi Chujo, D. Hirabayashi, Congbing Li, Yutaro Kobayashi, Junshan Wang, Haruo Kobayashi, Kentaroh Katoh, Sato Koshi","doi":"10.1109/IMS3TW.2014.6997393","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997393","url":null,"abstract":"This paper describes the architecture, implementation and measurement results for a Time-to-Digital Converter (TDC), with histogram-method self-calibration, for high-speed I/O interface circuit test applications. We have implemented the proposed TDC using a Programmable System-on-Chip (PSoC), and measurement results show that TDC linearity is improved by the self-calibration. All TDC circuits, as well as the self-calibration circuits can be implemented as digital circuits, even by using FPGA instead of full custom ICs, so this is ideal for fine CMOS implementation with short design time.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122168034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}