{"title":"Real-time correction of dc servo motor and controller failures using analog checksums","authors":"Suvadeep Banerjee, A. Chatterjee, J. Abraham","doi":"10.1109/IMS3TW.2014.6997391","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997391","url":null,"abstract":"Recently optimal controller design for real-time systems has been a prominent research focus for their application in intelligent autonomous systems. However, in the future it will be extremely important for real-time monitoring of safety-critical applications for their reliability. In this paper, we extend the theory for real-time compensation of transient errors and permanent faults in linear control systems derived from a low-overhead error detection scheme developed for plant-controller systems. The approach is demonstrated for transient error correction and parametric fault compensation on a servo-motor control application.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"734 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124015237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Grani, S. Bartolini, Emanuele Furdiani, L. Ramini, D. Bertozzi
{"title":"Integrated cross-layer solutions for enabling silicon photonics into future chip multiprocessors","authors":"P. Grani, S. Bartolini, Emanuele Furdiani, L. Ramini, D. Bertozzi","doi":"10.1109/IMS3TW.2014.6997403","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997403","url":null,"abstract":"Nanophotonic is a promising solution for interconnections in future chip multiprocessors (CMPs) due to its intrinsic low-latency and low-power features. This paper proposes an integrated approach with physical level design choices to select the most suitable optical network topology, and an adhoc software strategy to improve performance and reduce energy consumption of a tiled CMP architecture. We adopt an all-optical reconfigurable network which has been designed to significantly reduce path-setup latency and energy consumption. Specifically the optimization aims at distributing the traffic into the Network on Chip (NoC) in such a way to limit resurce usage conflicts (during path-setups) and have a more uniform utilization of the fast optical resources. On-chip photonics indeed is the key enabler for such a strategy permitting to reach even far destinations with a reduced latency, the same as the closest ones. We investigate performance/power consumption effects on a CMP system and we compare against both a high-performance electronic folded Torus NoC and the standard optical reconfigurable architecture. The optical network improves 7% on average over the electronic counterpart and, especially when using the dedicated software optimization for matching application locality and network features, it reaches about 26% average execution time improvement.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"9 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123703950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jorge Tonfat, J. Azambuja, G. Nazar, P. Rech, Fernanda Lima Kastensmidt, L. Carro, R. Reis, J. Benfica, F. Vargas, E. Bezerra, C. Frost
{"title":"Measuring the impact of voltage scaling for soft errors in SRAM-based FPGAs from a designer perspective","authors":"Jorge Tonfat, J. Azambuja, G. Nazar, P. Rech, Fernanda Lima Kastensmidt, L. Carro, R. Reis, J. Benfica, F. Vargas, E. Bezerra, C. Frost","doi":"10.1109/IMS3TW.2014.6997398","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997398","url":null,"abstract":"The susceptibility of SRAM-based FPGAs to soft errors increases with each technology node due to the reduction of transistor size, the reduction of voltage supply and the increase of density of devices. This work presents the actual impact of voltage reductions for neutron-induced soft errors in SRAM-based FPGAs. We run neutron radiation experiments with a Spartan-6 (45nm) FPGA at different supply voltages to measure the soft error susceptibility. We measure the variation of the susceptibility of the device (static test) and also of a functional system implemented in it (dynamic test). Experimental results show that 8% reduction in the VDD supply voltage can result in 30% higher device susceptibility. When this is translated to a functional system implemented in the FPGA, the system error rate can have a variation of 55% for a voltage variation of 19%, which has to be taken into account by the designer of the system.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127357273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Balen, R. G. Vaz, Gustavo S. Fernandes, E. R. Machado, O. Gonçalez
{"title":"Alternate Biasing Modular Redundancy: An alternative tolerance technique to cope with TID effects","authors":"T. Balen, R. G. Vaz, Gustavo S. Fernandes, E. R. Machado, O. Gonçalez","doi":"10.1109/IMS3TW.2014.6997402","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997402","url":null,"abstract":"In this work a novel radiation tolerance technique based on modular redundancy, associated to an alternated biasing scheme, is presented. The goal of this technique is to extend electronic systems lifetime in radiation environments for circuits that are susceptible to TID effects. In order to validate this technique, a board level prototype was built, considering an FPAA (Field Programmable Analog Array) as Device Under Test (DUT), to which the concept was applied. The prototype was exposed to Co60 gamma radiation with a dose rate of 1 krad(Si)/h. Results show that devices that are alternated biased are able to tolerate higher accumulated doses than the one that is permanently biased.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134262168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The influence of No Fault Found in analogue CMOS circuits","authors":"J. Wan, H. Kerkhoff","doi":"10.1109/IMS3TW.2014.6997388","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997388","url":null,"abstract":"The most difficult fault category in electronic systems is the “No Fault Found” (NFF). It is considered to be the most costly fault category in, for instance, avionics. The relatively few papers in this area rarely deal with analogue integrated systems. In this paper a simple simulation model has been developed for a particular type of NFF, the intermittent resistive fault resulting from bad interconnections. Simulations have been carried out with respect to a CMOS operational amplifier under influence of NFFs, and the resulting behaviour under different fault conditions has been examined.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121594244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. David-Grignot, F. Azais, L. Latorre, F. Lefèvre
{"title":"Stochastic model for phase noise measurement from 1-bit signal acquisition","authors":"S. David-Grignot, F. Azais, L. Latorre, F. Lefèvre","doi":"10.1109/IMS3TW.2014.6997400","DOIUrl":"https://doi.org/10.1109/IMS3TW.2014.6997400","url":null,"abstract":"This paper presents a novel method for phase noise measurement from 1-bit acquisition of an analog signal. A stochastic model is developed that permits to establish an analytical relationship between the phase noise level present in the analog signal and the characteristics of the binary data captured with a digital ATE. The technique is validated through both simulations and hardware measurements.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114018990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}