{"title":"Fault mitigation strategies for Single Event Transients on SAR converters","authors":"A. J. C. Lanot, T. Balen","doi":"10.1109/IMS3TW.2014.6997395","DOIUrl":null,"url":null,"abstract":"In this work, we analyze the resilience of SAR converters based on charge redistribution against Single Event Transients. These effects may be mitigated using well-known Fault Tolerance techniques. However, each strategy has its advantages and disadvantages, which may affect the area, power consumption, as well as the linearity of the circuit. This paper shows possible alternatives for the best trade-off approach on the design of such converters. Investigations were conducted by means of an extensive fault injection campaign in an 8-bit architecture modeled in SPICE, considering a 130nm predictive technology model.","PeriodicalId":166586,"journal":{"name":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","volume":"367 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"19th Annual International Mixed-Signals, Sensors, and Systems Test Workshop Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMS3TW.2014.6997395","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
In this work, we analyze the resilience of SAR converters based on charge redistribution against Single Event Transients. These effects may be mitigated using well-known Fault Tolerance techniques. However, each strategy has its advantages and disadvantages, which may affect the area, power consumption, as well as the linearity of the circuit. This paper shows possible alternatives for the best trade-off approach on the design of such converters. Investigations were conducted by means of an extensive fault injection campaign in an 8-bit architecture modeled in SPICE, considering a 130nm predictive technology model.