2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Stress-less Dicing Solution for Thin and Large Die Handling for 2.5D/3D IC Packaging","authors":"Sunwoo Park, Sujie Kang, Yong Shin, Nungpyo Hong, Hyun-Yong Lee, Kyungbin Lim, M. Rhee, Juho Jang, Jeongwon Oh, Sungsoon Park","doi":"10.1109/EPTC56328.2022.10013271","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013271","url":null,"abstract":"In this paper, ultra-thin die handling process and stress-less dicing are presented in the trend of light, thin, short and small semiconductor packages. As always there are pros and cons, the advanced component should be dealt with disadvantage of manufacturing and handling issue. Singluation of 20µm silicon die handling with glass carrier using stress-less dicing has been researched and laser modification chemical etching(LMCE) has been performed as a stress-less dicing solution. It is demonstrated that kerf width is able to be controlled by the number of laser modification scan from 30µm to 100µm. In addition, chemical and physical damage is not observed in the layer of adhesion and silicon thin die although glass carrier is etched away. The dicing represents superior and clear sawing line definition with minimum edge chipping. Consequently, laser modification chemical etching is considered as a stress-less dicing solution for ultra-thin die-level handling in 2.5D and 3D integrated circuit packaging.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125893200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical Modelling and Simulation of Plated Blowers for Cooling of Mobile Computing platforms","authors":"Shikhar Goel, Amit Kumar, Ratul Mali, Raghavendra Kanivihalli, S. Konakala, M. MacDonald, A. Bhattacharya","doi":"10.1109/EPTC56328.2022.10013295","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013295","url":null,"abstract":"In this paper, a novel design of centrifugal blower called Plated Blowers (PB) is proposed for cooling of laptop computers where the conventional rotor blade is replaced by a new design comprising of a sheet metal rotor with punched holes and residual hanging chads. A numerical study was conducted on these designs to determine the flow rates under operational speed of 6000 rpm. The results showed that the PB designs can outperform the traditional blade fan design as well as the Volumetric Resistance Blower (VRB) [1] in terms of air flow rate at iso-rpm conditions. Similar to VRB which has a porous rotor, the PBs are also expected to offer significant acoustic advantage over bladed fans (claim to be validated through tests), which can result in a boost in overall platform power in these mobile computing systems.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123848753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparative Study of Die-Attach Materials for LED Die Bonding","authors":"Liangxing Hu, Shuyu Bao, Yue Wang, Simon Chun Kiat Goh, Y. Lim, P. Zhao, Michael Joo Zhong Lim, Weiyang Miao, V. Q. Dinh, Sai Choo Tan, Kaihwa Chew, C. S. Tan","doi":"10.1109/EPTC56328.2022.10013260","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013260","url":null,"abstract":"In this work, the bonding conditions of different die-attach materials are optimized for LED die to substrate bonding. The die-attach materials are characterized for their mechanical bonding strength, hermeticity, and surface morphology. Among the investigated materials, it is found that SAC solder has the largest bonding strength of ~60 MPa. The hermeticity is at least 10× below the rejection limit of MIL-STD-883E standard (5×10−8 atm-cc/s) for all die-attach materials. The results show that high-quality bonding is achieved. Moreover, LEDs are fabricated and bonded onto substrate with die-attach materials. The electrical, electroluminescent, and photoluminescent properties of the un-bonded and bonded LEDs are investigated. The results reveal that non-conductive electrical adhesive has the least negative impact on the electrical property of LEDs, Ag paste has the largest positive effect on electroluminescent and photoluminescent properties. In addition, this comparative study can be used as guidelines to further optimize the process parameters, to characterize the material properties of die-attach materials (e.g. porosity, optical reflectance, volume resistivity, and thermal conductivity, etc.), and to study the effect of temperature on reliability luminous efficacy, and optical property of the packaged LEDs.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130301884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Risk Reduction Strategies for SiP Design and Manufacturing","authors":"Chaoran Yang, Yuan Zhang, Oscar Tang, Guneet Sethi, F. Song, MC Wong","doi":"10.1109/EPTC56328.2022.10013150","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013150","url":null,"abstract":"System-in-Package (SiP) technology provides a valuable opportunity to make products with smaller form factor, enrich functionality, and better reliability performance for consumer electronics. One key reason for SiP's success is the encapsulated structure using molding compound, which can provide protection to all the components inside and allows reduced component-to-component spacing. However, if the design or the manufacturing process have flaws, failures can also occur inside of SiP, and engineers have to spend more effort and time to conduct fault isolation, understand the root cause, and make related corrective actions. In this regard, failure risks not only occur at SiP module level. It can also happen in the final product level when assembled the SiP into it. Therefore, a comprehensive risk analysis, design and manufacturing assessment plan and an effective validation method at an early stage of the SiP development is extremely critical. This paper discusses two typical types of SiP failures. By using these two failure modes as an example, the methodology to identify and mitigate such risks early in the product development process will be demonstrated.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130417024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cu Wirebond Technology in 16FFC High Performance Automotive Radar Processor with IR Drop Reduction Methodology","authors":"Jasmine Lim, T. Tran, Y. K. Au, M. Song, Mollie Benson","doi":"10.1109/EPTC56328.2022.10013167","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013167","url":null,"abstract":"High performance automotive radar front-end processors normally use advanced semiconductor packaging such as Flip Chip, fan-in and fan-out wafer level Ball Grid Array (BGA) packages in order to provide superior performance in their applications. However, for a cost-effective package in the competitive business market, wirebonded package can also provide similar uncompromised performance. Advanced Cu wirebond technology was evaluated on the 16FFc radar processor. However, the challenge of high voltage drop, also known as IR drop, in 16FFc technology must be overcome. As wafer technology moves to smaller advanced nodes, the back-end-of-line (BEOL) metal thickness gets thinner, thus increasing the resistance per unit length. Another trend in semiconductor design has been a reduction in operating voltage, meaning that small changes in supply voltage may represent an increasing percentage of the digital swing and potentially lead to incorrect logic values. As current flows through a resistor, the high voltage drop could slow down the circuitry, impact the circuit timing and lead to functional failure. In order to reduce the IR drop in the radar processor when using Cu wirebond, a large quantity of intra-die wires was applied on the 16FFc silicon. IR drop simulation was performed on three layout conditions, 0%, 50% and 100% of the intra-die wires. Empirical data was also collected with actual Cu wirebonded samples. The fully populated intra-die wires reduced IR drop by 28%. To enable the reliable performance of the intra-die wires, Stand-off Stitch Bond (SSB) wirebond technology was introduced within the package. The development and reliability evaluation were conducted for Cu wirebonding on 16FFc automotive radar processor of 30mm2 die size in a 14mm x 14mm 2-layer substrate BGA package. Wirebond recipe was developed based on detailed Design of Experiment to establish bonding parameters for both standard wires and the intra-die wires. Packages were tested per AEC Grade 1 and AEC Q006 qualifications requirements. All results from package reliability assessments passed with no abnormality. Board level temperature cycling reliability for the BGA package with the four depopulated corner solder balls was evaluated with results surpassing our internal requirement for AEC Grade 1. This paper will present the results and analysis from (1) IR drop simulation and empirical data collection, (2) wirebond development and reliability of standard and intra-die wires on 16FFc Silicon, and (3) board level reliability of a BGA package with four depopulated corner solder balls.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127317615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Diebond Process Optimization and Surface Characterization to Eliminate Conductive Die Attach Film to Ag Plated Pad Delamination due to Intrinsic High Aspect Ratio Ultrathin Die Warpage and Bow Level","authors":"Marty Lorgino D. Pulutan, Olga Rivera","doi":"10.1109/EPTC56328.2022.10013112","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013112","url":null,"abstract":"Ultrathin wafers have intrinsic warpage and bow level due to residual stress during wafer fabrication and the acting gravitational force onto the unsupported weight of the wafer when placed in cassettes. The induced warpage on the parent wafer slice is translated into component dies during wafer sawing where additional stresses are introduced by the centrifugal force of rotating blade. Not only that high warpage and bow level increases the risk of die chipping and other sawing defects but also contribute to the poor adhesion of the die attach material to the adherend surface especially on the middle region where the maximum point of warpage and bowing is typically situated. The insufficient adhesion forms uneven gap on the interface which triggers non-uniform bondline thickness and consequently causes delamination. Reducing the warpage and bow level of the wafer has been the least option as package assembly process and wafer fabrication are two separate process and that limited solutions on wafer process and handling can be done due to thinness of the die. In this paper, the researchers identified solutions on the CDAF-to-Ag-plated surface interfacial delamination through diebond process optimization and surface characterization to arrive with appropriate leadframe material surface composition and optimized diebond parameters to offset the peeling stress from deflection of convex curvature of high aspect ratio ultrathin capacitor dies.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127394866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of Mechanical Properties of Nickel-Palladium Plated and Tin-Plated Copper Leadframe Material at Elevated Temperatures","authors":"Xintong Zhu, R. Rajoo, R. R. Nistala, Z. Mo","doi":"10.1109/EPTC56328.2022.10013296","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013296","url":null,"abstract":"In this paper the mechanical properties of Copper-based (Cu) leadframe with Tin (Sn) and Nickel-Palladium (NiPd) finishing are compared by using nano-indentation technique. Cu leadframes with the two types of finish materials are subjected to high temperature storage condition (HTS) of 150°C for 750 hours. Nano-indentations are performed at room temperature (25°C) and at elevated temperatures (125°C and 175°C), on samples before and after HTS, to compare the temperature response of the two leadframe finish materials. In the case of Sn plated leadframe, intermetallic compound formed influences its mechanical properties after HTS test. On the other hand, Ni crystalline grain properties (grain size and texture) and/or Ni inter-diffusion to Pd layer are of relevance for NiPd plated leadframe.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129096503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bonding with Zn-based solders through self-propagating exothermic reaction to enable high-temperature electronics packaging","authors":"Canyu Liu, Hanqing Jiang, S. Liang, Allan Liu, Zhaoxia Zhou, Chang Liu","doi":"10.1109/EPTC56328.2022.10013226","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013226","url":null,"abstract":"With the growing interest in Wide Band Gap (WBG) devices that can operate under higher temperatures (≥250°C), there is an imperative demand to develop advanced bonding processes and materials to meet the reliability requirements. In the current work, self-propagating exothermic reaction (SPER) has been applied to assist the bonding based on Zn-based solders. With the Zn-based solder precoated on various electronic components, bonding is achieved at the Ni/Al nanofoil/solder interface experimentally. The simulation results show that the maximum melting thickness of solder decreased with the increase of substrate thickness. When Si die was applied, nanofoil exhibited the best bonding strength with solder. Preheating is beneficial to expand the melting thickness of solder. The experimental results confirmed the predicted results from the simulation, which can be potentially used for high-temperature electronics packaging.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127981883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal and RF Characterization of Novel PLA/Flax Based Biodegradable Printed Circuit Boards","authors":"A. Géczy, András Csiszár, P. Xavier, N. Corrao, D. Rauly, R. Kovács, Anna Fehér, Egon Rozs, L. Gál","doi":"10.1109/EPTC56328.2022.10013255","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013255","url":null,"abstract":"In this study, a novel printed circuit board (PCB) substrate made of polylactic acid (PLA) reinforced with flame-retarted flax fibers is presented as a biodegradable substitute for conventional PCB materials, which is compatible with traditional subtractive technology and SMT assembling, so that the present and future trends in green electronics could fit in the well-established packaging processes. The current paper focuses on thermal and RF characterization of the materials, with the addition of environmental analysis based on pilot antennas. Finally new promising path for improved quality is presented. It was found that the thermal diffusivity of the material mainly depends on the PLA in the composite, where the values are in good agreement with the ones that can be found in the literature regarding the base material. The RF characterization shows, that the RF losses are better than paper-based substrates. The paper reveals that from the aspect of environmental impact, such assemblies can be considered better than ones manufactured from traditional substrates, but worse than e.g. paper-based electronics. The paper also reveals a future path with a promising new generation of the PLA/flax boards, leading to similar build qualities as on traditional FR4 boards.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129527521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"EOS-induced failure analysis of FPGAs","authors":"Yan Huang, Panpan Jiang, Tianhan Liu, Chaohui Liang","doi":"10.1109/EPTC56328.2022.10013170","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013170","url":null,"abstract":"In this article, EOS-induced failures of three FPGAs due to the severe voltage over or under shoots during debugging process are analyzed, based on well designed procedures. The traditional techniques used are capable to pinpoint and characterize the details of EOS-induced failures, this may assist the manufacturers and users to do the provenance-tracking and improve the reliability of FPGAs application.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129689674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}