2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)最新文献_第8页

Package Failure Understanding Through Crack Propagation Analysis 通过裂纹扩展分析来理解包装失效

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013304

Dexter delos Santos, Jefferson Talledo, Mark Renier Santos

引用次数: 0

A Study on Combination of ENEPIG Surface Finish and Solder Ball for Solder Joint Reliability ENEPIG表面光洁度与焊锡球相结合提高焊点可靠性的研究

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013300

Geondu Gim, Jong-beom Park, Hunju Lim, Gook-Yong Jung

{"title":"A Study on Combination of ENEPIG Surface Finish and Solder Ball for Solder Joint Reliability","authors":"Geondu Gim, Jong-beom Park, Hunju Lim, Gook-Yong Jung","doi":"10.1109/EPTC56328.2022.10013300","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013300","url":null,"abstract":"An electroless nickel (Ni)/electroless palladium (Pd)/immersion gold (Au) (ENEPIG) surface finish is widely applied to substrates used in various semiconductor packages. However, many issues have been arising in terms of solder joint reliability (SJR) during the assembly process. A number of factors can affect SJR such as thickness of each layer of ENEPIG, reflow profile, plating bath conditions, chemical composition of Pd and Ni layer, and chemical composition of solder balls. This paper focuses on investigating the influence of the factors on SJR and formation of intermetallic compounds (IMCs). The present study investigated the effect of the number of reflows (1, 3 and 5), Ni and Pd thickness of ENEPIG (Ni: 3, 6 and 9 µm, Pd: 0.02, 0.06 and 0.1 µm), chemical composition of Pd layer (pure Pd and Pd-phosphorus (P)) and chemical composition of solder balls (tin (Sn)0.7copper (Cu), SAC305 (Sn3.0 silver (Ag) 0.5Cu), SAC302 (Sn3.0Ag0.2Cu) and Sn3.5Ag). Special focus involved the combination of solder balls (SAC305 and Sn3.5 Ag) and chemical composition of the Pd layer (pure Pd and Pd-P). SJR that were evaluated through pull test and shear test, and then IMCs were observed through scanning electron microscope (SEM) analysis. The effect of Pd and Ni thickness with Pd-P and pure Pd was confirmed. Compared to Pd-P ENEPIG, a relatively high risk of SJR was found when using solder ball with no or low Cu content (e.g., SAC302 and Sn3.5Ag) and pure Pd ENEPIG. As a result of SEM analysis, Kirkendall voids were observed in the Ni2SnP IMC layer only on pure Pd ENEPIG with Sn3.5Ag solder balls and the fracture occurred along the void line. For Sn3.5Ag, a thicker P-rich layer (around 700 µm) was formed compared to SAC305 (300µm).","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130156347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Numerical Simulation for Flow Boiling in Microchannels with Different Pin Fin Arrays 不同引脚鳍阵列微通道内流动沸腾的数值模拟

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013261

Liang Hongying, Pan Lunsheng, L. Jing, Zhang Xiaowu, Le Ducvinh, Cheng Ming, Li Jun, K. C. Wei, Chui King Jien, Feng Huicheng

引用次数: 1

One-sided directional slot antenna with magnetic film for 28 GHz application 单面定向槽天线带磁膜，用于28ghz应用

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013140

Koto Miyahara, Takeshi Ishibashi, K. Tham, K. Goodwill, H. Kanaya

引用次数: 0

Enhancement of Vacuum Reflow Process for CCPAK - A Solution to Oxidized Lead Frame 氧化引线架CCPAK - A溶液真空回流工艺的改进

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013269

Ramices Sanchez, Joshua Manguiat, Francis Louise Fajardo

{"title":"Enhancement of Vacuum Reflow Process for CCPAK - A Solution to Oxidized Lead Frame","authors":"Ramices Sanchez, Joshua Manguiat, Francis Louise Fajardo","doi":"10.1109/EPTC56328.2022.10013269","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013269","url":null,"abstract":"With the development of high-power packages as a solution to customer needs and requirements, the CCPAK was introduced to fill the performance gap. A GaN (Gallium Nitride) is packaged with a silicon FET (Field Effect Transistor) and integrated with copper clip technology. This complex technology required process development, especially for the die attach clip attach process. In the initial CCPAK DACA characterization, visible evidence of lead frame oxidation was noted at the vacuum reflow process. As excessive lead frame oxidation is detrimental to package integrity and unlikely to occur in a vacuum state, the team decided to employ the DMAIC approach in systematically resolving this issue. Process elimination was conducted to pin down the problematic process from through the SIPOC diagram to understand, identify, and describe the failure. Monthly occurrence of oxidized lead frame was examined. Simulations were executed to validate the most possible cause of oxidation, which was the displacement of carrier on the heater block during the reflow process. Characterization was conducted, focusing on control of carrier movement during process. Initial results and prolonged performance were monitored. With the appropriate solution in placed, full elimination of lead frame oxidation was achieved resulting to yield improvement. Furthermore, the importance of proper process development prior production release was given emphasis.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114883291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Overlay Diagnostics of Die-to-die Alignment on the Kulicke and Soffa LITEQ 500 Stepper Kulicke和sofa LITEQ 500步进机模对模叠加诊断

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013124

S. Misat, M. Loktev, R. Schiedon, Jeroen de Boeij, M. van der Stam, Chia–Ching Huang, P. Sixt, Haidar Al Dujaili, T. Dewolf, N. Allouti, L. Pain, C. Vannuffel, P. Coudrain, A. Garnier

{"title":"Overlay Diagnostics of Die-to-die Alignment on the Kulicke and Soffa LITEQ 500 Stepper","authors":"S. Misat, M. Loktev, R. Schiedon, Jeroen de Boeij, M. van der Stam, Chia–Ching Huang, P. Sixt, Haidar Al Dujaili, T. Dewolf, N. Allouti, L. Pain, C. Vannuffel, P. Coudrain, A. Garnier","doi":"10.1109/EPTC56328.2022.10013124","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013124","url":null,"abstract":"Fan-Out Wafer Level Packaging (FO-WLP) [1], [2] is one of the key packaging solutions in present-day IC manufacturing. One of its main challenges is chip placement error, which occurs during wafer reconstruction and molding. In subsequent lithographic processing steps, i.e., forming of the redistribution layer, it is important to align to individual dies instead of performing global alignment per wafer to meet the overlay target. Previously we reported the implementation of die-to-die alignment using the LITEQ 500 lithographic projection stepper from Kulicke & Soffa [3]. This process is evaluated experimentally in collaboration between Kulicke & Soffa and CEA LETI. Accurate measurement of the resulting overlay error represents another challenge due to varying rotation and translation. In this paper we describe two different methods for overlay measurement in the LITEQ 500 tool, one developed specifically for this application case. Both methods are applied for characterizing test wafers, yielding largely similar results. The measured overlay error of four test wafers is well within the 500 nm range.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132362793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parametric study on relevant design and material parameters for reliable hard encapsulation of automotive power modules 汽车电源模块可靠硬封装相关设计及材料参数的参数化研究

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013218

M. Sprenger, Niklas Noll, Christoph Hecht, Malte de Greiff, Lars Müller, J. Franke

{"title":"Parametric study on relevant design and material parameters for reliable hard encapsulation of automotive power modules","authors":"M. Sprenger, Niklas Noll, Christoph Hecht, Malte de Greiff, Lars Müller, J. Franke","doi":"10.1109/EPTC56328.2022.10013218","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013218","url":null,"abstract":"In power module packaging, the standard approach for encapsulation is potting by soft silicone gels with low vis-cosity and youngs modulus. Within the last decade, hard encapsulation realized by large area transfer-molding of epoxy mold compounds has established itself as an alternative due to potential cost reduction and reliability enhancement. Large-area potting of liquid hard encapsulant material is another option for realization of a hard encapsulation. Regardless of the used process technology the large substrate, heatsink and module size in general, multi-material stack-up, heavy cyclic thermal loads during operation, high temperature and high voltage operation possess challenges to the material choice for hard encapsulation. Delamination and brittle fracture of the encapsulant and damage of the encapsulated structure through the encapsulant are the main concerns within the material selection process. Thermo-mechanical simulations can support and provide guidance within this material selection process. Therefore comparative parametric simulations have been performed within this study in order to estimate the influences of geometric parameters, such as substrate metallization thickness and heatsink thickness, and process parameters, such as curing temperature of the potting material, onto the thermo-mechanical behavior of the encapsulated packages. The concept of calculating an “effective package coefficient of thermal expansion” is introduced in this study as a tool for effective selection of encapsulants. The obtained results can be used as a guideline for the selection of encapsulation materials for different module stack ups.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128430488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Process variations in dielectric inserted side contact multilayer graphene nanoribbon interconnects using montecarlo simulations 采用蒙特卡罗模拟研究介电插入侧接触多层石墨烯纳米带互连的工艺变化

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013293

Mekala Girish Kumar, Yash Agrawal, Vobulapuram Ramesh Kumar

引用次数: 0

An effective analytical method for thermal stresses analysis of heterogeneous integration system in display 为显示器非均质集成系统热应力分析提供了一种有效的分析方法

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013197

Sixin Huang, Haohui Long, Jianhui Li

{"title":"An effective analytical method for thermal stresses analysis of heterogeneous integration system in display","authors":"Sixin Huang, Haohui Long, Jianhui Li","doi":"10.1109/EPTC56328.2022.10013197","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013197","url":null,"abstract":"The heterogeneous integration system in display (HiSID) is a brand new architecture in accordance with the demand and technology trends of the next generation terminal device, and the new development architecture consists of multi-interactive function units are applied to solve the issue of non-fully-utilized area on the display module. However, the technologies challenge of thermal management increase when these interactive components are integrated into display modular system. Especially, the reliability of HiSID model are often affected by the temperature change due to the mismatch of coefficients of thermal expansion (CTE) and elastic modulus among functional components, solders, and substrate. In this paper, an effective analytical model is systematically established to promptly simulate the thermal shock performance to verify and further discuss the reliability of HiSID structure, and it is different from traditional finite element method. The total strains of entire HiSID models are decomposed into the uniform strain and bending strain, and the bending strain of segmented solder joints are modified. And the longitudinal stresses of each component are calculated based on the product of Young's modulus and total strains. The interfacial stress along the heterogeneous interfaces are expressed as exponential stress function, which satisfy the variation tendency from free-edge to the position away from the boundary. The inner stresses and interfacial stresses induced by temperature change from present analytical method are also validated against those results of the finite element method. Moreover, the FR4-based and glass-based substrate for HiSID model are compared to demonstrate the better thermal-mechanical behaviors.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116778427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of Die Thickness on the Reliability of Solder Joint in Clip-bonded Packages 模具厚度对夹焊封装焊点可靠性的影响

2022 IEEE 24th Electronics Packaging Technology Conference (EPTC) Pub Date : 2022-12-07 DOI: 10.1109/EPTC56328.2022.10013243

Ilyas Dchar, Ding Yandoc

{"title":"Effect of Die Thickness on the Reliability of Solder Joint in Clip-bonded Packages","authors":"Ilyas Dchar, Ding Yandoc","doi":"10.1109/EPTC56328.2022.10013243","DOIUrl":"https://doi.org/10.1109/EPTC56328.2022.10013243","url":null,"abstract":"Thin die is more and more widely used in power packages for automotive applications due to their lower electrical resistance and better thermal dissipation. For thin wafers, die pickup operation is a critical aspect in the assembly manufacture process. The use of inappropriate tape stickiness and ejection parameter settings can cause microcracks that can eventually lead to die cracking. Increasing die thickness may be an alternative solution to reduce die cracks ppm issues (by increasing the mechanical strength of the die). Obviously, the increase of die thickness will result again to high die resistance. Additionally., thicker die may worsen the thermal fatigue behavior of the die attach solder. The scope of this study is to confirm the impact of solder joints fatigue behavior in clip bonded package using different die thicknesses by subjecting devices to temperature cycling (TC) and thermal fatigue tests (IOL/TFT). Furthermore, simulations and visual inspection using cross-sectioning were used to inspect the die attach degradation on various samples after aging tests. This study also provides a vital information of the relationship between solder degradation and different die thicknesses, which can be used as reference for future wafer thickness reduction programs to achieve a better product RDSon.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122101630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1