Overlay Diagnostics of Die-to-die Alignment on the Kulicke and Soffa LITEQ 500 Stepper

Abstract

Fan-Out Wafer Level Packaging (FO-WLP) [1], [2] is one of the key packaging solutions in present-day IC manufacturing. One of its main challenges is chip placement error, which occurs during wafer reconstruction and molding. In subsequent lithographic processing steps, i.e., forming of the redistribution layer, it is important to align to individual dies instead of performing global alignment per wafer to meet the overlay target. Previously we reported the implementation of die-to-die alignment using the LITEQ 500 lithographic projection stepper from Kulicke & Soffa [3]. This process is evaluated experimentally in collaboration between Kulicke & Soffa and CEA LETI. Accurate measurement of the resulting overlay error represents another challenge due to varying rotation and translation. In this paper we describe two different methods for overlay measurement in the LITEQ 500 tool, one developed specifically for this application case. Both methods are applied for characterizing test wafers, yielding largely similar results. The measured overlay error of four test wafers is well within the 500 nm range.