Process variations in dielectric inserted side contact multilayer graphene nanoribbon interconnects using montecarlo simulations

Abstract

Dielectric inserted side contact multilayer graphene nanoribbon (DSMLGNR) interconnect is envisaged as one of the prominent solutions for on-chip global interconnects. The tremendous growth in nanofabrication technology processes and huge number of transistors on a very large scale integrated (VLSI) silicon chip have made process-induced variations in devices and interconnects quite prominent. To investigate these variations a driver-interconnect-load system is considered in the present work. The impact of device and interconnect parameter variability on the electrical performance of on-chip DSMLGNR interconnect system is analyzed. The Monte Carlo analyses for propagation delay and power dissipation are performed using HSPICE simulations for DSMLGNR interconnects.