{"title":"由于固有的高纵横比超薄模具翘曲和弯曲水平,以消除导电模贴膜到镀银垫上分层的Diebond工艺优化和表面表征","authors":"Marty Lorgino D. Pulutan, Olga Rivera","doi":"10.1109/EPTC56328.2022.10013112","DOIUrl":null,"url":null,"abstract":"Ultrathin wafers have intrinsic warpage and bow level due to residual stress during wafer fabrication and the acting gravitational force onto the unsupported weight of the wafer when placed in cassettes. The induced warpage on the parent wafer slice is translated into component dies during wafer sawing where additional stresses are introduced by the centrifugal force of rotating blade. Not only that high warpage and bow level increases the risk of die chipping and other sawing defects but also contribute to the poor adhesion of the die attach material to the adherend surface especially on the middle region where the maximum point of warpage and bowing is typically situated. The insufficient adhesion forms uneven gap on the interface which triggers non-uniform bondline thickness and consequently causes delamination. Reducing the warpage and bow level of the wafer has been the least option as package assembly process and wafer fabrication are two separate process and that limited solutions on wafer process and handling can be done due to thinness of the die. In this paper, the researchers identified solutions on the CDAF-to-Ag-plated surface interfacial delamination through diebond process optimization and surface characterization to arrive with appropriate leadframe material surface composition and optimized diebond parameters to offset the peeling stress from deflection of convex curvature of high aspect ratio ultrathin capacitor dies.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Diebond Process Optimization and Surface Characterization to Eliminate Conductive Die Attach Film to Ag Plated Pad Delamination due to Intrinsic High Aspect Ratio Ultrathin Die Warpage and Bow Level\",\"authors\":\"Marty Lorgino D. Pulutan, Olga Rivera\",\"doi\":\"10.1109/EPTC56328.2022.10013112\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Ultrathin wafers have intrinsic warpage and bow level due to residual stress during wafer fabrication and the acting gravitational force onto the unsupported weight of the wafer when placed in cassettes. The induced warpage on the parent wafer slice is translated into component dies during wafer sawing where additional stresses are introduced by the centrifugal force of rotating blade. Not only that high warpage and bow level increases the risk of die chipping and other sawing defects but also contribute to the poor adhesion of the die attach material to the adherend surface especially on the middle region where the maximum point of warpage and bowing is typically situated. The insufficient adhesion forms uneven gap on the interface which triggers non-uniform bondline thickness and consequently causes delamination. Reducing the warpage and bow level of the wafer has been the least option as package assembly process and wafer fabrication are two separate process and that limited solutions on wafer process and handling can be done due to thinness of the die. In this paper, the researchers identified solutions on the CDAF-to-Ag-plated surface interfacial delamination through diebond process optimization and surface characterization to arrive with appropriate leadframe material surface composition and optimized diebond parameters to offset the peeling stress from deflection of convex curvature of high aspect ratio ultrathin capacitor dies.\",\"PeriodicalId\":163034,\"journal\":{\"name\":\"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-12-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPTC56328.2022.10013112\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC56328.2022.10013112","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Diebond Process Optimization and Surface Characterization to Eliminate Conductive Die Attach Film to Ag Plated Pad Delamination due to Intrinsic High Aspect Ratio Ultrathin Die Warpage and Bow Level
Ultrathin wafers have intrinsic warpage and bow level due to residual stress during wafer fabrication and the acting gravitational force onto the unsupported weight of the wafer when placed in cassettes. The induced warpage on the parent wafer slice is translated into component dies during wafer sawing where additional stresses are introduced by the centrifugal force of rotating blade. Not only that high warpage and bow level increases the risk of die chipping and other sawing defects but also contribute to the poor adhesion of the die attach material to the adherend surface especially on the middle region where the maximum point of warpage and bowing is typically situated. The insufficient adhesion forms uneven gap on the interface which triggers non-uniform bondline thickness and consequently causes delamination. Reducing the warpage and bow level of the wafer has been the least option as package assembly process and wafer fabrication are two separate process and that limited solutions on wafer process and handling can be done due to thinness of the die. In this paper, the researchers identified solutions on the CDAF-to-Ag-plated surface interfacial delamination through diebond process optimization and surface characterization to arrive with appropriate leadframe material surface composition and optimized diebond parameters to offset the peeling stress from deflection of convex curvature of high aspect ratio ultrathin capacitor dies.