Chaoran Yang, Yuan Zhang, Oscar Tang, Guneet Sethi, F. Song, MC Wong
{"title":"Risk Reduction Strategies for SiP Design and Manufacturing","authors":"Chaoran Yang, Yuan Zhang, Oscar Tang, Guneet Sethi, F. Song, MC Wong","doi":"10.1109/EPTC56328.2022.10013150","DOIUrl":null,"url":null,"abstract":"System-in-Package (SiP) technology provides a valuable opportunity to make products with smaller form factor, enrich functionality, and better reliability performance for consumer electronics. One key reason for SiP's success is the encapsulated structure using molding compound, which can provide protection to all the components inside and allows reduced component-to-component spacing. However, if the design or the manufacturing process have flaws, failures can also occur inside of SiP, and engineers have to spend more effort and time to conduct fault isolation, understand the root cause, and make related corrective actions. In this regard, failure risks not only occur at SiP module level. It can also happen in the final product level when assembled the SiP into it. Therefore, a comprehensive risk analysis, design and manufacturing assessment plan and an effective validation method at an early stage of the SiP development is extremely critical. This paper discusses two typical types of SiP failures. By using these two failure modes as an example, the methodology to identify and mitigate such risks early in the product development process will be demonstrated.","PeriodicalId":163034,"journal":{"name":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE 24th Electronics Packaging Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC56328.2022.10013150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
System-in-Package (SiP) technology provides a valuable opportunity to make products with smaller form factor, enrich functionality, and better reliability performance for consumer electronics. One key reason for SiP's success is the encapsulated structure using molding compound, which can provide protection to all the components inside and allows reduced component-to-component spacing. However, if the design or the manufacturing process have flaws, failures can also occur inside of SiP, and engineers have to spend more effort and time to conduct fault isolation, understand the root cause, and make related corrective actions. In this regard, failure risks not only occur at SiP module level. It can also happen in the final product level when assembled the SiP into it. Therefore, a comprehensive risk analysis, design and manufacturing assessment plan and an effective validation method at an early stage of the SiP development is extremely critical. This paper discusses two typical types of SiP failures. By using these two failure modes as an example, the methodology to identify and mitigate such risks early in the product development process will be demonstrated.