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2016 International Symposium on Integrated Circuits (ISIC)最新文献

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Fully integrated pseudo differential K-band power amplifier in 0.13um standard CMOS 全集成伪差分k波段功率放大器在0.13um标准CMOS
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829728
Pengwei Chen, Jin He, Jiang Luo, Hao Wang, Sheng Chang, Qijun Huang, Hao Yu, Xiao-peng Yu
{"title":"Fully integrated pseudo differential K-band power amplifier in 0.13um standard CMOS","authors":"Pengwei Chen, Jin He, Jiang Luo, Hao Wang, Sheng Chang, Qijun Huang, Hao Yu, Xiao-peng Yu","doi":"10.1109/ISICIR.2016.7829728","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829728","url":null,"abstract":"A K-band power amplifier (PA) module with on-chip input and output matching network was fabricated in standard 130-nm CMOS process with 1.5-V supply voltage. The fully integrated PA module consists of 2-stage pseudo-differential cascode configuration PA and on-chip stacked balun based on transformer. At 26GHz, the PA achieved 18.6-dB small-signal gain, 12.2-dBm saturated output power and 22.4% power added efficiency (PAE). The chip occupies an area of 0.88 × 0.62mm2, including all the dc and RF pads.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133993620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.2–2.5 GHz CMOS power amplifier using transformer-based broadband matching network 基于变压器宽带匹配网络的0.2-2.5 GHz CMOS功率放大器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829732
Daming Ren, Zhi-xiong Ren, Ke-feng Zhang, X. Zou, Wei Zou, Yang Yu
{"title":"A 0.2–2.5 GHz CMOS power amplifier using transformer-based broadband matching network","authors":"Daming Ren, Zhi-xiong Ren, Ke-feng Zhang, X. Zou, Wei Zou, Yang Yu","doi":"10.1109/ISICIR.2016.7829732","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829732","url":null,"abstract":"A 0.2∼2.5 GHz broadband CMOS power amplifier (PA) for a wireless transceiver is designed using 180 nm CMOS process. Considering the difficulty of integration, this PA is divided into a high-band PA (1.2∼2.5 GHz) and a low-band one (0.2∼1.2 GHz). The high-band PA achieves all components integrated on-chip by using transformer-based matching network and the low-band one adopts off-chip matching network in order to obtain optimal performance. The S11 of the PA is less than −10 dB and the maximum S21 achieves 15.13 dB at 0.5 GHz. From 0.2 GHz to 2.5 GHz, the PA shows a maximum output power of 22.42 dBm, a peak power added efficiency (PAE) of 23.3 % and the power gain more than 10.44 dB. When the input power is less than 0 dBm, the IMD3 is decreased blow −25 dBc. The total chip size of the PA is 1.23×1.96 mm2 and it consumes 230 mA from the 3.3 V supply voltage.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132266211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Online unsupervised structural plasticity algorithm for multi-layer Winner-Take-All with binary synapses 二元突触多层赢者通吃的在线无监督结构塑性算法
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829691
Subhrajit Roy, He Tong, A. Basu
{"title":"Online unsupervised structural plasticity algorithm for multi-layer Winner-Take-All with binary synapses","authors":"Subhrajit Roy, He Tong, A. Basu","doi":"10.1109/ISICIR.2016.7829691","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829691","url":null,"abstract":"This article introduces a novel hardware friendly multi-layer Winner-Take-All (WTA) architecture using neurons with nonlinear dendrites and binary synapses. The network is trained by an unsupervised spike based learning rule that modifies the network connections. Inspired by the multi-layer models of human visual cortex, the proposed architecture contains multiple layers of neurons. We show that if we increase the synaptic time constant of the layers of the system in succession, it is capable of inspecting the incoming patterns for a longer duration of time before providing a decision. After the training is complete, a unique neuron of the last layer emits a spike for same class of patterns. The results discussed in this article show that the proposed structural plasticity based WTA is capable of classifying Poisson spike trains and the two layer structure provides a 2% and a 38% increase in performance for two different tasks when sufficient neurons are employed. Moreover, compared to conventional architectures, our method is far more memory efficient for high dimensional inputs (input dimension > 200).","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126557362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Safety across the HW/SW interface - Can formal methods meet the challenge? 跨硬件/软件接口的安全性——形式化方法能否应对挑战?
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829707
C. Bartsch, Carlos Villarraga, D. Stoffel, W. Kunz
{"title":"Safety across the HW/SW interface - Can formal methods meet the challenge?","authors":"C. Bartsch, Carlos Villarraga, D. Stoffel, W. Kunz","doi":"10.1109/ISICIR.2016.7829707","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829707","url":null,"abstract":"In the design of Systems-on-Chip and Embedded Systems measures for increasing their error resilience can benefit from a precise understanding of the effects that hardware (HW) faults may have on the execution of the system's software (SW). This is true in particular for low-level software components controlling the communication between the application software and the hardware, implementing important functions for chip management and, not rarely, replacing traditionally hardware-implemented control functions of the system. Also safety functions are often implemented in low-level software and rely on a well-defined interaction between hardware and software, even in the case of HW errors. Safety functions are specified traces of behavior by which the system must respond under certain inputs or in case of internal errors.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125883489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.18µm, 0.6V, 83.5µW integer DCT processor for neural signal applications 用于神经信号应用的0.18µm, 0.6V, 83.5µW整数DCT处理器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829680
T. Tang, W. Goh, Xin Liu, Chao Wang
{"title":"A 0.18µm, 0.6V, 83.5µW integer DCT processor for neural signal applications","authors":"T. Tang, W. Goh, Xin Liu, Chao Wang","doi":"10.1109/ISICIR.2016.7829680","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829680","url":null,"abstract":"Neural recording is one of the most noteworthy technologies in today's world, where large amount of recorded neural signal over prolonged duration consumes hefty time and energy for data transmission. During the past decade, the discrete cosine transform (DCT) has been used for data compression in bio-medical application due to its high energy efficiency. In this paper, a multiplication-free integer DCT processor based on a parallel-pipelined architecture is proposed. The novel integer DCT processor utilizes a parallel structure to reduce the latency to 6 clock cycles as compared to the conventional hardware design. Ultra-low-voltage operation is adopted to improve the energy efficiency together with parallel processing. The new integer DCT processor is implemented on 0.18-µm CMOS process with 0.6-V supply voltage and it can achieve a DCT transform in 240 ns with power consumption of only 83.5 µW at 25 MHz, making it suitable for multi-channel wireless neural signal processing application.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129933520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A rail-to-rail noise-shaping non-binary SAR ADC 一种轨对轨噪声整形非二进制SAR ADC
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829678
S. Saisundar, N. Yoshio, Kah-Hyong Chang
{"title":"A rail-to-rail noise-shaping non-binary SAR ADC","authors":"S. Saisundar, N. Yoshio, Kah-Hyong Chang","doi":"10.1109/ISICIR.2016.7829678","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829678","url":null,"abstract":"This paper presents a 10-bit, 5.12 kS/s noise-shaping non-binary successive approximation ADC (SAR ADC). The proposed noise-shaping SAR ADC requires an additional capacitor and a buffer along with a non-binary SAR ADC to implement the first order noise-shaping of the quantization error. The structure operates with a rail-to-rail input and yields a very high dynamic range of about 89.3dB. This is a novel approach to garner the advantages of noise-shaping along with the higher effective number of bits (ENOB) offered by a non-binary SAR ADC. The design also implements a 2-stage cascaded integrator comb decimation filter. The ADC implemented in a 0.18µm CMOS process occupies an active area of 0.31mm2. It achieves a good differential non-linearity of less than ±0.48LSB and integral non-linearity of less than ±0.9LSB. With a −0.5dBFS input signal the ADC obtains an SNDR of 88dB in 40Hz bandwidth after decimation. This corresponds to an ENOB of 14.3. The ADC requires about 20µW power from a 1.8V supply leading to a Figure of Merit (FoM) of 151dB.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A continuous switching mode step-down switched-capacitor regulator with inrush current control scheme 一种带涌流控制方案的连续开关降压开关电容稳压器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829697
Chengyue Yu, Xiang Zhang, L. Siek
{"title":"A continuous switching mode step-down switched-capacitor regulator with inrush current control scheme","authors":"Chengyue Yu, Xiang Zhang, L. Siek","doi":"10.1109/ISICIR.2016.7829697","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829697","url":null,"abstract":"Switched-capacitor based regulator has its unique usage in various power management applications where both small foot print and flexible current capability is required since the switched-capacitor power stage is scalable with current rating and thus opens possibility of fully on-chip implementation whereas inductor based regulator is very limited by inductor size due to the only availability of off-chip inductor that can be used by relatively low switching frequency regardless of current capability. Thus switched-capacitor based regulator is very suitable for IoT application, where multiple power rail is needed but PCB size is very limited and external components are limited. In this paper, a ½ step-down power stage is introduced, analyzed. Furthermore, problem with the phenomena associated with switched-capacitor regulators is described and the scheme to overcome the issue. A full regulator architecture that regulates the inrush current is introduced and simulation results shows that the output ripple is greatly reduced compared to an open loop step down switched-capacitor power stage.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128075714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VCO-based ADCs for IoT applications 用于物联网应用的基于vco的adc
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829746
Vishnu Unnikrishnan, M. Vesterbacka, A. Alvandpour
{"title":"VCO-based ADCs for IoT applications","authors":"Vishnu Unnikrishnan, M. Vesterbacka, A. Alvandpour","doi":"10.1109/ISICIR.2016.7829746","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829746","url":null,"abstract":"Internet of things (IoT) benefits from fast and low cost development of technology portable re-configurable hardware. Low power consumption is desired for applications operating from harvested or limited energy. Subthreshold operation of VCO-based ADCs is investigated in this work in order to meet these challenges. A ring VCO built using NAND gates is used for reliable operation in the subthreshold region. The impact of supply scaling and PVT variations on the VCO characteristics as well as on the converter performance is studied using transistor level simulations. Some solutions are suggested towards energy efficient operation over a wide range of PVT conditions.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114315936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
DC-50 GHz low loss switch matrix design in high resistivity trap-rich SOI 高阻富阱SOI中dc - 50ghz低损耗开关矩阵设计
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829704
Boa-Hua Yu, Kaixue Ma, F. Meng, Bharatha Kumar Thangarasu, K. Yeo
{"title":"DC-50 GHz low loss switch matrix design in high resistivity trap-rich SOI","authors":"Boa-Hua Yu, Kaixue Ma, F. Meng, Bharatha Kumar Thangarasu, K. Yeo","doi":"10.1109/ISICIR.2016.7829704","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829704","url":null,"abstract":"This paper presents low insertion loss, high isolation, ultra wideband (DC to 50 GHz) 2 × 2 switch matrix in a 300mm 0.13 µ m high substrate resistivity trap-rich SOI. The switches are designed by using a series-shunt-series configuration with input and output matching networks. The designed switches achieve a 1.8 dB of low insertion loss and a high isolation of 38 dB up to 50 GHz. 1dB-compression point of designed switches are larger than 19 dBm from DC to 50 GHz. The active chip area of designed 2 × 2 switch matrix is only 0.28 × 0.21 mm2.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Performance analysis on active rectifier structures for inductively powered application 电感供电有源整流器结构的性能分析
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829700
Q. Low, Mi Zhou, L. Siek
{"title":"Performance analysis on active rectifier structures for inductively powered application","authors":"Q. Low, Mi Zhou, L. Siek","doi":"10.1109/ISICIR.2016.7829700","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829700","url":null,"abstract":"In this study, two active rectifier structures which are the full-wave rectifier and the two-stage rectifier for inductively powered application are analyzed and presented. This paper provides a precise analysis on the differences between the two structures and investigates the best load condition for the maximal performance in each of the structures respectively. Mathematical equations are derived to model the power losses and the power conversion efficiency. Moreover, the estimated values from the derived equations are shown to be tallied with the simulation results. Both of the structures are fabricated in standard CMOS 0.18µm AMS process. Simulation results show that they achieve a peak efficiency of 96.8% and 97.4% respectively at the frequency of 125 kHz with varying AC amplitude of 1.2V–2.5V.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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