A 0.18µm, 0.6V, 83.5µW integer DCT processor for neural signal applications

Abstract

Neural recording is one of the most noteworthy technologies in today's world, where large amount of recorded neural signal over prolonged duration consumes hefty time and energy for data transmission. During the past decade, the discrete cosine transform (DCT) has been used for data compression in bio-medical application due to its high energy efficiency. In this paper, a multiplication-free integer DCT processor based on a parallel-pipelined architecture is proposed. The novel integer DCT processor utilizes a parallel structure to reduce the latency to 6 clock cycles as compared to the conventional hardware design. Ultra-low-voltage operation is adopted to improve the energy efficiency together with parallel processing. The new integer DCT processor is implemented on 0.18-µm CMOS process with 0.6-V supply voltage and it can achieve a DCT transform in 240 ns with power consumption of only 83.5 µW at 25 MHz, making it suitable for multi-channel wireless neural signal processing application.