{"title":"Synchronous Electric Charge Extraction for low voltage Piezoelectric Energy Harvester array","authors":"Arish Shareef, W. Goh, Yuan Gao, S. Narasimalu","doi":"10.1109/ISICIR.2016.7829690","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829690","url":null,"abstract":"This paper introduces a topology to combine multiple low voltage Piezoelectric Energy Harvesters with the goal of widening its harvestable frequency range and improving the power output. The architecture uses a shared inductor scheme and a rectifier-free approach. The proposed harvester is able to handle multiple harvesters efficiently by harvesting the peak energy from each harvester. The proposed topology and its circuit implementation has been validated using SPICE simulation. The circuit consumes about 2.6 µA @ 3V per energy harvester and is capable of harvesting energy from low voltage sources down to 0.4Vpk.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of monolithic I/Q based impedance measurement circuits: Impact of non-ideal circuit effects on accuracies","authors":"Yan Hong, Yong Wang, W. Goh, Yuan Gao, Lei Yao","doi":"10.1109/ISICIR.2016.7829682","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829682","url":null,"abstract":"I/Q demodulation technique is widely used in monolithic circuits for impedance measurement. The measurement accuracy of impedance is vital for various biomedical applications. The measurement accuracies of the impedance based on the I/Q demodulation was reported around 2%. This paper serves to investigate degradation of measurement accuracy due to non-ideal circuit effects, such as DC components in stimulation currents, offset of amplifiers and frequency-dependent gain in amplifier as well as angular deviation of the I/Q signals. The measurement errors due to the non-ideal effects of practical analog circuits are evaluated mathematically. The errors are quantified in terms of the real part (Er) and imaginary part (Ei) of the impedance. From the results, we gathered that the errors in the real and imaginary parts are both proportional to gain fluctuation. With angular derivation of the I/Q signals from −9° to 9° and an impedance phase difference of 1° to 89°, Er is noted to vary from −6.6% to 4.15%. On the other hand, Ei is noted to range from −896% to 894%. In circuit implementation, the measured Er is around 1%. As for the imagery part, the measurement accuracy suffers greatly, even up to 109% with just 1° angular deviation of the I/Q signals. The findings here are beneficial for impedance measurement circuitry design, providing a clear instruction on how to enhance the measurement accuracies.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117279321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect","authors":"Maoxiang Yi, Yingxian Gan, Zhengfeng Huang, Huaguo Liang","doi":"10.1109/ISICIR.2016.7829675","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829675","url":null,"abstract":"In this paper, a new NMOS transistor aging model is proposed, in which the positive bias temperature instability (PBTI) and hot carrier injection (HCI) effects are jointly considering and a W-value is defined to express the impact of stacking of NMOS transistors on the transistors input signal probability and switching activity. An input reordering scheme is proposed to mitigate PBTI and HCI induced CMOS circuit aging. Experimental results on typical CMOS gate circuits show that the error of the aging delay time obtained by our model with that by HSPICE simulation is less than 2%, and the circuit lifetime can be increased by 13.2% on average by using our scheme.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124802547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Highly secured arithmetic hiding based S-Box on AES-128 implementation","authors":"Ali Akbar Pammu, Kwen-Siong Chong, B. Gwee","doi":"10.1109/ISICIR.2016.7829736","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829736","url":null,"abstract":"We propose an arithmetic hiding technique on Advanced Encryption Standard (AES) algorithm implementation to highly secure the algorithm against Side-Channel Attack (SCA). The arithmetic operations run parallel with Substitution-Box (S-Box) operation of the AES to hide the correlated leakage power dissipation with processed data. There are two key features in our proposed hiding technique. First, the function of the arithmetic hiding is independent with S-Box operation and its power dissipation is dominant over the S-Box. Therefore, the dependency of the total power dissipation with processed data in the AES algorithm is relatively low. Second, the security level of proposed technique against SCA based on Correlation Power Analysis (CPA) and Correlation Electromagnetic Analysis (CEMA) attack are increased by 119× and 63× respectively, compared with unprotected S-Box. This is due to the leakage physical parameters (i.e. power dissipation and EM emanation) which is generated by the arithmetic operation hides the leakage parameters of the S-Box operation. Based on the measurement results on Sakura-X FPGA board, which performs AES-128 algorithm, our proposed technique dissipates 3.8mW and features 1.18× higher power dissipation than the unprotected S-Box implementation. However, our proposed arithmetic hiding technique is highly secured, as the result of CPA and CEMA attack require 38,000 power traces and 44,000 EM traces respectively to reveal the secret key. The required number of traces are significantly higher than the unprotected S-Box, which is only 319 power traces and 691 EM traces respectively to uncover the same secret key.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115566242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kai Tang, Y. Zhang, Bo Chen, Liheng Lou, Yong Wang, Yuanjin Zheng
{"title":"An analog baseband chain of synthetic aperture radar receiver","authors":"Kai Tang, Y. Zhang, Bo Chen, Liheng Lou, Yong Wang, Yuanjin Zheng","doi":"10.1109/ISICIR.2016.7829717","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829717","url":null,"abstract":"An analog baseband chain for a synthetic aperture radar (SAR) receiver is presented in this paper. The proposed analog baseband chain consists of a 12th-order bandpass filter (BPF) and a five-stage programmable gain amplifier (PGA). The BPF is composed of six cascaded Biquads and the switched-RC arrays are used to enable digital control of the passband in a frequency range from 0.68 to 9 MHz. The PGA employs binary-weighted switching array as pseudo-exponential function to achieve large dynamic range. Under 6-bit control words, the gain of the chain can be controlled and has a dB-linear gain range of 60 dB from 10.47 to 69.63 dB with a gain error of less than ±0.39 dB. This analog baseband chain has been implemented in 65 nm CMOS technology embedding in a SAR receiver. The analog baseband occupies 0.35 mm2 silicon area and consumes less than 16 mA current from a 1.2 V supply.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116287197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jian Sen Teh, A. R. Palaniappan, L. Siek, Yuanjin Zheng
{"title":"Review of pulse generators for gated ring oscillator based Time-to-Digital converters","authors":"Jian Sen Teh, A. R. Palaniappan, L. Siek, Yuanjin Zheng","doi":"10.1109/ISICIR.2016.7829703","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829703","url":null,"abstract":"Pulse generator serves an important role in gated ring oscillator (GRO) based Time-to-Digital converters (TDC) to enable the ring oscillator for the input time difference between two reference timing events. As the resolution of TDC advances to a few picoseconds, the linearity of the pulse generator becomes increasingly important. This paper reviews and compare between pulse generators implemented using a XOR gate, SR latch, phase frequency detector (PFD) and time difference generator (TDG). Simulation results in standard 40nm CMOS technology shows that the TDG is the most suitable pulse generator since it has the best linearity. In terms of power and area, the dynamic PFD is a good alternative.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131799654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On determining optimal parameters for testing devices against laser fault attacks","authors":"J. Breier, Chien-Ning Chen","doi":"10.1109/ISICIR.2016.7829727","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829727","url":null,"abstract":"Laser equipment has been used for a failure analysis for a long time. It is also becoming increasingly popular in fault injection attacks. Since it can be challenging to master this technique and get plausible results from experimental evaluations, in this paper we provide a set of guidelines and best practices that might help researchers to get the basic idea on this topic. First, we describe different decapsulation techniques with details on de-packaging steps. After that, we provide insights on choosing the right laser setup for laser fault injection. Finally, we provide hands-on experience on device profiling for making the attack successful.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127589066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Aiming for the cloud - a study of implanted battery-free temperature sensors using NFC","authors":"J. Wikner, Johan Zötterman, A. Jalili, S. Farnebo","doi":"10.1109/ISICIR.2016.7829739","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829739","url":null,"abstract":"In this paper we present results based on measurements of implantable devices which can be powered externally and communicated with using the near-field communication (NFC) infrastructure. NFC allows us to not have a dedicated gateway and intra-body communication to bridge the data from sensors to phone. In our trials, we have used commercially available sub-components and mounted them on a thin plastic with printed interconnections and coated them for bio-compatibility. Devices were implanted in porcine models during one week. We could during this time measure the in-vivo body temperature through skin and subcutaneous tissue ranging in thickness from some mm to a couple of cm. The implanted sensor devices are mounted on thin, printed-electronics plastic sheets where the coils and conductors are designed with different types of materials. The choice of materials is done in order to offer a low-cost solution to read out data from in-vivo sensors. We compile measured data, practical results and guidelines, together with theoretical results referring to the design of the implanted inductive NFC coil as well as the energy transfer from one mobile device to another.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114654110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Concurrent device/circuit aging for general reliability simulations","authors":"Haoyuan Jiang, Chenyue Ma, Lining Zhang, M. Chan","doi":"10.1109/ISICIR.2016.7829708","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829708","url":null,"abstract":"Continuous shrinking of design window for circuit reliability requires more accurate aging simulation tools. In this paper we describe one concurrent device/circuit aging method for general reliability simulations with improved accuracy. Several circuit reliability mechanisms under modern design concepts are described first, including the negative bias temperature instabilities (NBTI), the self-heating effect on reliability and the electromigration (EM) with design schemes such as dynamic voltage and frequency scaling. The aging simulation methodology currently being used is reviewed, which is inefficient in handling these emerging reliability problems. One possible solution, the dynamic time evolution method (DTEM), is introduced which supports the concurrent device and circuit aging simulations. It is shown that DTEM reproduces the complex reliability behaviors in the transistor level and provides a general framework for isolated or coupled reliability mechanisms in the circuit level.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"There ain't no plain key: A PUF based first-order side-channel resistant encryption construction","authors":"Marc Stöttinger, Bernhard Jungk","doi":"10.1109/ISICIR.2016.7829738","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829738","url":null,"abstract":"The confidentiality of all modern symmetric encryption schemes relies on the sealing of the secret key. Hence, it is crucial to secure the secret key or other sensitive credentials in protected memory such as a secure key storage. An alternative to a key storage is a physical unclonable function, which generates a unique secret key for each device online. But still, the secret might leak during intermediate processing when used in an encryption scheme. In this paper, we propose a encryption scheme, which uses keys generated by a blinded PUF. The unmasking of these keys is done during the encryption operation of the block cipher, instead of directly after key generation. As a side effect the entire scheme provides resistance against first-order power analysis attacks while only public credentials are need to be stored.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125817596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}