Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect

Abstract

In this paper, a new NMOS transistor aging model is proposed, in which the positive bias temperature instability (PBTI) and hot carrier injection (HCI) effects are jointly considering and a W-value is defined to express the impact of stacking of NMOS transistors on the transistors input signal probability and switching activity. An input reordering scheme is proposed to mitigate PBTI and HCI induced CMOS circuit aging. Experimental results on typical CMOS gate circuits show that the error of the aging delay time obtained by our model with that by HSPICE simulation is less than 2%, and the circuit lifetime can be increased by 13.2% on average by using our scheme.