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2016 International Symposium on Integrated Circuits (ISIC)最新文献

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A low phase noise wideband VCO with 8-shaped inductor 带8形电感的低相位噪声宽带压控振荡器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829733
Wei Zou, Zhi-xiong Ren, Ke-feng Zhang, X. Zou, Daming Ren, Dapeng Zou
{"title":"A low phase noise wideband VCO with 8-shaped inductor","authors":"Wei Zou, Zhi-xiong Ren, Ke-feng Zhang, X. Zou, Daming Ren, Dapeng Zou","doi":"10.1109/ISICIR.2016.7829733","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829733","url":null,"abstract":"This paper presents a wideband voltage-controlled oscillator (VCO) with 8-shaped inductor for multi-band wireless communication system. The 8-shaped coils serve to reduce inductive crosstalk. The whole circuit is fully designed and simulated using 180nm CMOS technology process. The VCO provides the tuning range (TR) of 37.2% from 3.61 GHz to 5.26 GHz. The single-side phase noise at 1MHz offset are −129.5 dBc/Hz and −123.7 dBc/Hz at minimum and maximum frequencies, respectively. By adopting a 7-bit switched body-grounded NMOS varactor array with one reverse-biased diode varactor pair, the low VCO gain (less than 43 MHz/V) is achieved in whole tuning range. The layout occupies 0.32×0.46 mm2 and consumes 15 mA from the 1.8 V supply.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"88 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131676517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Ku-band high-isolation SPDT switch in 0.35um SiGe BiCMOS technology 采用0.35um SiGe BiCMOS技术的ku波段高隔离SPDT开关
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829686
Wenju Li, Kaixue Ma, Shouxian Mou
{"title":"A Ku-band high-isolation SPDT switch in 0.35um SiGe BiCMOS technology","authors":"Wenju Li, Kaixue Ma, Shouxian Mou","doi":"10.1109/ISICIR.2016.7829686","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829686","url":null,"abstract":"In this paper, a compact high isolation 14–18 GHz SPDT switch using triple-well transistors based on 0.35µm SiGe BiCMOS process is proposed. Improved series-shunt-shunt topology is used in this design to increase the isolation and to reduce the insertion loss concurrently. In order to improve the power handling capability, body-floating technique is employed and analyzed. The simulation results shown that in the interested frequency band of 14–18 GHz, the insertion loss of the ON state path is better than 1.5 dB, and the isolation of the OFF state path is higher than 44dB. The P1dB of the ON state path at center frequency 15.5 GHz is 13dBm, and the chip size is 0.125 mm2.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131758432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low complexity 60-GHz receiver architecture for simultaneous phase and amplitude regenerative sampling systems 同时相位和幅度再生采样系统的低复杂度60ghz接收机结构
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829729
T. Girg, Daniel Schrüfer, M. Dietz, A. Hagelauer, D. Kissinger, R. Weigel
{"title":"Low complexity 60-GHz receiver architecture for simultaneous phase and amplitude regenerative sampling systems","authors":"T. Girg, Daniel Schrüfer, M. Dietz, A. Hagelauer, D. Kissinger, R. Weigel","doi":"10.1109/ISICIR.2016.7829729","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829729","url":null,"abstract":"With increasing data rates in communication systems, the call for wideband transceiver solutions capable of processing complex modulation schemes is getting stronger. Unfortunately, this goes along with power hungry systems and more complex integrated circuits. A novel receiver architecture, which addresses these issues, is based on the simultaneous phase and amplitude regenerative sampling system. Its system exploits switched injection-locked oscillators and their capability to regenerate signals with a gain of over 40 dB. This paper demonstrates an integrated solution for phase demodulation in such an architecture. The proposed concept uses the low complex but efficient self-mixing principle and consists mainly of double-balanced Gilbert mixers, amplifiers, a delay line and passive power dividers. The detection of the phase is achieved through self-mixing the regenerated signal with one path delayed by a symbol period. The architecture achieves 2 GBaud/s with 8th order differential phase shift keying at a frequency of 60 GHz and is realized in a 130nm SiGe BiCMOS technology.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131728664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modelling of high frequency Lamb wave resonator for monolithic CMOS radar transceiver 单片CMOS雷达收发器高频Lamb波谐振器建模
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829718
Yong Wang, Yuanjin Zheng, X. Mu
{"title":"Modelling of high frequency Lamb wave resonator for monolithic CMOS radar transceiver","authors":"Yong Wang, Yuanjin Zheng, X. Mu","doi":"10.1109/ISICIR.2016.7829718","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829718","url":null,"abstract":"A pure and high-frequency clock reference will benefit the radar transceivers, helping on generating superior chirp signals. Revealed by recent literatures, Lamb-wave resonator is a candidate to provide such a reference. However, reported equivalent-circuit models of Lamb wave resonators are not accurate enough to enable the designs of integrated circuits. This paper discusses necessities of high-frequency resonators for radar transceivers, measures to design CMOS compatible Lamb-wave resonator for monolithic transceiver implementations, the importance of accurate modeling. An accurate model is also put forward that can precisely fit the two-port Y-parameters of the fabricated device. This work is very useful for radar transceiver designs, oscillator designs, and also device analysis.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Millimeter wave transformer coupled low-power and broadband power amplifiers 毫米波变压器耦合低功率和宽带功率放大器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829719
Bo Chen, Liheng Lou, Kai Tang, Jianjun Gao, Yuanjin Zheng
{"title":"Millimeter wave transformer coupled low-power and broadband power amplifiers","authors":"Bo Chen, Liheng Lou, Kai Tang, Jianjun Gao, Yuanjin Zheng","doi":"10.1109/ISICIR.2016.7829719","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829719","url":null,"abstract":"This paper presents two millimeter wave PAs realized in a 130 nm CMOS process. The power amplifier adopts transformer and transmission line matching topology which achieves small area and broadband. One power amplifier focus on low power and the other focus on broadband. The low-power power amplifier operates from 1.2 V supply with 10 dB gain at 62 GHz, and dissipates 58 mW DC power. Reverse isolation is better than 39 dB from 50 GHz to 75 GHz. The measured 3 dB bandwidth of the broadband power amplifier is 20 GHz (from 47 GHz to 67 GHz); the measured maximum gain is 8.6 dB; output 1 dB compression power is 9.36 dBm and consumes 90 mA current from 1.2 V DC supply. Including its pads, the PA occupies a compact chip area of 0.318 mm2, and without pads, the PA occupies 0.141 mm2.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128743361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 65nm CMOS ping-pong auto-zero resistance-to-frequency converter for resistive bridge sensors 一种用于电阻桥式传感器的65nm CMOS乒乓型自动归零电阻-频率转换器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829730
Y. Li, K. C. Koay, P. K. Chan
{"title":"A 65nm CMOS ping-pong auto-zero resistance-to-frequency converter for resistive bridge sensors","authors":"Y. Li, K. C. Koay, P. K. Chan","doi":"10.1109/ISICIR.2016.7829730","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829730","url":null,"abstract":"A low energy-noise switched-capacitor (SC) interface with low offset for resistive bridge sensor in 65nm CMOS technology is presented. It converts the resistance imbalance of the bridge sensor into a saw-tooth frequency using current-mode sensing technique. Auto-zero (AZ) technique incorporating with ping-pong architecture is proposed to reduce the offset and low-frequency noise of the amplifier. The AZ SC amplifier achieves a temperature coefficient of 0.016 µV/°C from −40 °C to 90 °C whilst the input offset displays less than 100µV. Compared to conventional counterpart without the AZ technique, it offers significant lower offset and offset drift at the tradeoff for the increase of power. The sensor interface consumes 337 µW at a 1.2 V single supply and displays excellent energy-noise FOM with respect to other representative reported works.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130790337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Switch size control circuit in wide-load PWM/PFM DC-DC buck converters 宽负载PWM/PFM DC-DC降压变换器开关尺寸控制电路
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829740
B. Yuan, X. Lai, Jun Wang, Yao Huang, Xiuzhi Wu
{"title":"Switch size control circuit in wide-load PWM/PFM DC-DC buck converters","authors":"B. Yuan, X. Lai, Jun Wang, Yao Huang, Xiuzhi Wu","doi":"10.1109/ISICIR.2016.7829740","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829740","url":null,"abstract":"A switch size control circuit for voltage-mode DC-DC buck converter is presented. By detecting the average load current, the circuit not only achieves hybrid mode of PWM and PFM operation, but also changes the power switch size according to the load conditions. Both the high-side and low-side switch currents are fully sensed by detecting the filtered smooth voltage of the switch node. The generated digital signal maintains a substantially constant mode and switch size changing point. A monolithic DC-DC buck converter using the proposed circuit has been fabricated with a 0.5µm CMOS process for validation. The switch size is 1/3 of the maximum value in PFM operation and changes to full size in PWM operation. High efficiency over a wide load current from 0.001 to 5A is achieved. The measurement result shows that the switch size control circuit has good performance and agrees well with the theoretical analysis.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124276704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low voltage 2-stage and 3-stage push-pull output amplifiers in 65-nm CMOS technology 低压2级和3级推挽输出放大器在65纳米CMOS技术
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829714
U. Dasgupta
{"title":"Low voltage 2-stage and 3-stage push-pull output amplifiers in 65-nm CMOS technology","authors":"U. Dasgupta","doi":"10.1109/ISICIR.2016.7829714","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829714","url":null,"abstract":"A new low-voltage push-pull output stage is proposed. It can be adapted for use in low-voltage two-stage or multi-stage amplifiers. A 2-stage amplifier and a 3-stage amplifier were fabricated using this output stage in a 65-nm CMOS process with threshold voltages of 0.35V for p-channel and 0.5V for n-channel devices. Silicon measurements show both the amplifiers are able to operate with a power supply voltage range of 0.7V to 1.5V. Detailed simulation and measurement results that compare the performances of the two amplifiers are provided when stand-alone as well as in an application.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129284733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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