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2016 International Symposium on Integrated Circuits (ISIC)最新文献

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Half-bridge driver with charge pump based high-side voltage regulator 半桥驱动器与电荷泵为基础的高压侧稳压器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829724
Jun Yu, K. Chai, Yat-Hei Lam, M. A. Arasu
{"title":"Half-bridge driver with charge pump based high-side voltage regulator","authors":"Jun Yu, K. Chai, Yat-Hei Lam, M. A. Arasu","doi":"10.1109/ISICIR.2016.7829724","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829724","url":null,"abstract":"This paper presents a half-bridge driver to fulfill the requirement for interfacing with MEMs sensors. The upper switch of the driver is implemented by a p-type power transistor to make the driver feasible for pulse density modulated input signal. The high-side “ground” reference voltage V<inf>SSH</inf> is regulated through the proposed charge pump circuit, which harvests the charges flowing into the V<inf>SSH</inf> node and boosts them to the supply of the power stage V<inf>HV</inf>. The charge pump is designed with reversion loss prevention function to achieve a voltage difference close to V<inf>DD</inf> between V<inf>HV</inf> and V<inf>SSH</inf>. The driver is fabricated using the 0.18-µm CMOS process with 24-V LDMOS devices. The measurement results confirm the validation of the half-bridge driver with power efficiency up to 95%.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129680266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
What happens on an MPSoC stays on an MPSoC - unfortunately! 不幸的是，MPSoC上发生的事情会留在MPSoC上!
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829711
Philipp Wagner, Lin Li, Thomas Wild, A. Mayer, A. Herkersdorf
{"title":"What happens on an MPSoC stays on an MPSoC - unfortunately!","authors":"Philipp Wagner, Lin Li, Thomas Wild, A. Mayer, A. Herkersdorf","doi":"10.1109/ISICIR.2016.7829711","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829711","url":null,"abstract":"Software diagnosis on MPSoCs, the process of finding functional bugs or performance inefficiencies in complex hardware-software systems, is challenging. As both software and hardware complexity grow, the software observability decreases. At the same time, understanding the intended software behavior has become more difficult. We present an integrated approach which combines domain-specific representations of how software should execute on a specific processor microarchitecture, with a flexible diagnosis infrastructure to verify the assumptions through on-chip observations. It increases observability by preprocessing observation data to useful information on-chip, which can be transferred off-chip easier.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121466531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS digital-controlled oscillator for All-digital PLL frequency synthesizer 用于全数字锁相环频率合成器的CMOS数字控制振荡器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829720
Liheng Lou, Bo Chen, Kai Tang, Yuanjin Zheng
{"title":"A CMOS digital-controlled oscillator for All-digital PLL frequency synthesizer","authors":"Liheng Lou, Bo Chen, Kai Tang, Yuanjin Zheng","doi":"10.1109/ISICIR.2016.7829720","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829720","url":null,"abstract":"A broadband CMOS digital-controlled oscillator (DCO) for All-digital PLL (ADPLL) frequency synthesizer was developed, which achieves wide tuning range and low phase noise. The DCO employs a LC Voltage-controlled oscillator (VCO) and a current-steering Digital-to-Analog Convertor (DAC). In order to lower the VCO phase noise while fulfill continuous tuning range of 2GHz, P-type AMOS varactors are used, which connect to LC tank through a MIM coupling capacitor. As a digital interface, the DAC adopts dynamic element matching (DEM) and high speed ΣΔ modulation for mitigating the current source mismatch and enhance the frequency resolution, respectively. This DCO is implemented in a 65 nm CMOS RF technology. The test results show that, consuming 19.8mW under a 1.2 V supply, the proposed DCO can be tuned from 13.69 GHz to 15.93 GHz and exhibits phase noise of −99dBc/Hz at 1 MHz offset from the 15 GHz carrier in the ADPLL frequency synthesizer. The core LC VCO figure-of-merit (FoM) of −169.6dBc/Hz and FoMT of −173.1dBc/Hz are achieved.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121618082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter 用于可变增益放大器或滤波器的基于mosfet的电子可调谐电阻
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829715
W. L. Tan, C. H. Chang, L. Siek
{"title":"Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter","authors":"W. L. Tan, C. H. Chang, L. Siek","doi":"10.1109/ISICIR.2016.7829715","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829715","url":null,"abstract":"We present a new design of an electronically tunable linear MOS resistor circuit that operates in the subthreshold saturation region, supported with mathematical derivations and simulation results using CSM0.13µm technology. For a given potential difference across the MOS resistor, its gate voltage will be automatically biased through feedback to provide the correct amount of current based on the desired resistance set through the bias current. In comparison with an existing design [1], the proposed design offers equal tunabilty with 36 less transistors for unidirectional current and 28 less transistors with one more bias current transistor for bidirectional current. A bias current ranging between 10nA to 100nA offers a tunable linear resistance between 20MΩ to 140MΩ.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120957454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of metal work function on the DC characteristics of an asymmetric MOSFET with Schottky-based source 金属功函数对肖特基源非对称MOSFET直流特性的影响
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829713
A. Ajaykumar, Xing Zhou, S. B. Chiah
{"title":"Effect of metal work function on the DC characteristics of an asymmetric MOSFET with Schottky-based source","authors":"A. Ajaykumar, Xing Zhou, S. B. Chiah","doi":"10.1109/ISICIR.2016.7829713","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829713","url":null,"abstract":"Schottky Source (S) and Drain (D) based MOSFETs have been extensively studied in the past. These devices are tunneling based and show improved short channel effects and reduced contact resistance. In this paper we study the effect of S metal work function (ΦM) on the carrier injection process and its impact on the subthreshold swing and ON-OFF current ratio in an asymmetric n-type MOSFET. We show that by carefully tuning the ΦM, tunneling to thermionic injection transition is possible. Asymmetric MOSFETs also show improved OFF current due to reduced hole injection from the drain contact.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
28nm latch type sense amplifier coupling effect analysis 28nm锁存式感测放大器耦合效应分析
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829751
Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang, Aiming Ji, L. Mao
{"title":"28nm latch type sense amplifier coupling effect analysis","authors":"Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang, Aiming Ji, L. Mao","doi":"10.1109/ISICIR.2016.7829751","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829751","url":null,"abstract":"With development of semiconductor fabrication technology, channel length of CMOS device and device pitch scale down accompanied by more severe process variation and signal coupling effect. In this paper, we focus on the decouple latch type voltage sense amplifier which is widely used in SRAM product. Two main signal coupling effects are introduced and analyzed, and improved design is suggested","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131180681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An interchip Power Line Communication 芯片间电力线通信
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829743
Paulo Marcos Pinto, T. Pimenta, R. Moreno, Odilon O. Dutra, Rodrigo A. S. Braga
{"title":"An interchip Power Line Communication","authors":"Paulo Marcos Pinto, T. Pimenta, R. Moreno, Odilon O. Dutra, Rodrigo A. S. Braga","doi":"10.1109/ISICIR.2016.7829743","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829743","url":null,"abstract":"Dense wired networks, such as ultra-dense EEG network, comprised of 256 or 512 electrodes for temporal and spatial analysis of the brain, demand a large amount of wiring. Instead of using a pair of wires for power supply and additional wiring for communication, the use of Power Line Communications (PLC) allows power and communication in a single pair of wires. In this project, we propose a transceiver (transmitter and receiver) 0.18µm CMOS technology, for a 1.8V power supply operating at 10 MHz. Simulations conducted on CADENCE (Virtuoso Analog Design Environment L Editing) demonstrate the circuit is capable of transmitting and receiving data properly.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131270155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An implementation of analytical power model on integrated GPU 分析功率模型在集成GPU上的实现
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829731
Ning Li, Li Shen, Qingnhua Zhu, Yemao Xu, Jialong Wang, Zhiying Wang
{"title":"An implementation of analytical power model on integrated GPU","authors":"Ning Li, Li Shen, Qingnhua Zhu, Yemao Xu, Jialong Wang, Zhiying Wang","doi":"10.1109/ISICIR.2016.7829731","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829731","url":null,"abstract":"GPU has become an important component of the high performance computing system and its principal duty is parallel computing rather than graphical display. Determining the power and energy consumption is necessary to the scaling of GPU. This paper presents a statistic model to evaluate the power and energy consumption of AMD's integrated GPU (iGPU). By collecting the data of performance counters from real hardware measurements, we apply linear regression method to estimate the energy consumed by iGPU. Our results show that the median absolute error is less than 3%. Due to the limits of profiling tool CodeXL, power sampling period is much longer than the kernel execution time. We propose a kernel extension method to lengthen the kernel execution time so that we can deal with this problem. Furthermore, we conduct a study on the importance of performance counters and explore the possibility to simplify our statistic model. The results suggest that the accuracy and stability is still acceptable when there are only 12 performance counters in the simplified model.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128057804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wideband digital variable gain amplifier with DC offset cancellation in SiGe 0.18µm BiCMOS technology 一种采用SiGe 0.18µm BiCMOS技术的宽带数字可变增益放大器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829702
Muting Lu, Bharatha Kumar Thangarasu, Dawei Zhang, Xiaopeng Yu, K. Yeo
{"title":"A wideband digital variable gain amplifier with DC offset cancellation in SiGe 0.18µm BiCMOS technology","authors":"Muting Lu, Bharatha Kumar Thangarasu, Dawei Zhang, Xiaopeng Yu, K. Yeo","doi":"10.1109/ISICIR.2016.7829702","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829702","url":null,"abstract":"This paper presents a five-stage wideband digital controlled variable gain amplifier (DVGA). A bandwidth extended technique is proposed in this design to enhance gain flatness and enlarge gain range in high operating frequency. DC offset cancellation in this design helps to enhance the performance of proposed DVGA. The design is simulated using a commercial 0.18µm SiGe BiCMOS technology. The DVGA has a simulated gain range of 64.7 dB with a 3-dB bandwidth from 3 MHz to 3.55 GHz, an output 1-dB gain compression point better than −5.2 dBm, an input return loss better than 11.9 dB, an output return loss better than 18 dB, and a dc power consumption for core DVGA circuit of 3.7 mW from a 1.8-V supply.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fast-response buck-boost DC-DC converter with constructed full-wave current sensor 带全波电流传感器的快速响应降压-升压DC-DC变换器
2016 International Symposium on Integrated Circuits (ISIC) Pub Date : 2016-12-01 DOI: 10.1109/ISICIR.2016.7829745
Lei Zhu, Biao Chen, Yanqi Zheng, Jianping Guo, M. Ho, K. Leung, Dihu Chen, Yang Liu
{"title":"A fast-response buck-boost DC-DC converter with constructed full-wave current sensor","authors":"Lei Zhu, Biao Chen, Yanqi Zheng, Jianping Guo, M. Ho, K. Leung, Dihu Chen, Yang Liu","doi":"10.1109/ISICIR.2016.7829745","DOIUrl":"https://doi.org/10.1109/ISICIR.2016.7829745","url":null,"abstract":"A comparator-based current mode control buck-boost DC-DC converter with low transition noise full-wave current sensor is reported in this work. The proposed comparator-based current mode control method with on-time modulation eliminates the controller delay in constant on/off time period during load transient, which is adopted in a buck-boost DC-DC converter to achieve faster load transient responses. Benefited from the combination of SenseFET-based and filter-based current sensing, the proposed constructed current sensor is free from large spiking during state transition between high-side and low-side power transistor current sensing. Moreover, its dc accuracy will not drift due to the dc resistance (DCR) of the inductor as in the conventional filter-based inductor current sensor.","PeriodicalId":159343,"journal":{"name":"2016 International Symposium on Integrated Circuits (ISIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121910191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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